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Found 6 publication records. Showing 6 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
41 | Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra |
Power Consumption of Fault Tolerant Busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 542-553, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra |
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 76-86, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques |
39 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 685-688, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
39 | Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen |
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 114-119, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault-tolerant, reliability, low power, coupling capacitance |
18 | Alok Agrawal, Rajesh Gupta 0002 |
Coordinated Control of Hybrid DERs Enabled Grid-Interactive Residential PCM With Hybrid Bus Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Syst. J. ![In: IEEE Syst. J. 16(3), pp. 4607-4618, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Atul Katoch, Harry J. M. Veendrick, Evert Seevinck |
High speed current-mode signaling circuits for on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4138-4141, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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