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Searching for phrase bus-layout (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996 (1) 2005 (1) 2006 (1) 2008 (2) 2022 (1)
Publication types (Num. hits)
article(3) inproceedings(3)
Venues (Conferences, Journals, ...)
ICCAD(1) IEEE Des. Test Comput.(1) IEEE Syst. J.(1) IEEE Trans. Very Large Scale I...(1) ISCAS (4)(1) ISPD(1)
Authors
André K. Nieuwland(2) Cecilia Metra(2) Daniele Rossi 0001(2) Alok Agrawal(1) Atul Katoch(1) Chun-Chih Chen(1) Edwin Naroska(1) Evert Seevinck(1) Harry J. M. Veendrick(1) Kanad Chakraborty(1) Pinaki Mazumder(1) Rajesh Gupta 0002(1) Richard P. Kleihorst(1) Shanq-Jang Ruan(1) Steven V. E. S. van Dijk(1)
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
41Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra Power Consumption of Fault Tolerant Busses. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra Simultaneous Switching Noise: The Relation between Bus Layout and Coding. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
39Kanad Chakraborty, Pinaki Mazumder An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing
39Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF fault-tolerant, reliability, low power, coupling capacitance
18Alok Agrawal, Rajesh Gupta 0002 Coordinated Control of Hybrid DERs Enabled Grid-Interactive Residential PCM With Hybrid Bus Layout. Search on Bibsonomy IEEE Syst. J. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
10Atul Katoch, Harry J. M. Veendrick, Evert Seevinck High speed current-mode signaling circuits for on-chip interconnects. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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