Search results for "carry-save-adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
119	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
102	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
84	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
66	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
66	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
63	Taewhan Kim, William Jao, Steven W. K. Tjiang	Circuit optimization using carry-save-adder cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
55	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
47	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
47	Daniel E. Atkins, Shauchi Ong	Time-Component Complexity of Two Approaches to Multioperand Binary Addition.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
44	Melika Amiri, Massoud Dousti, Majid Mohammadi	Design and implementation of carry-save adder using quantum-dot cellular automata.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
44	Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini	An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
44	Debashis De, Jadav Chandra Das	Design of novel carry save adder using quantum dot-cellular automata.	J. Comput. Sci.	2017	DBLP DOI BibTeX RDF
44	Song Jia, Shigong Lyu, Xiayu Li, Li Liu, Yandong He	Simplified carry save adder-based array multiplier scheme and circuits design.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
44	Stefan Siegel, Jürgen Wolff von Gudenberg	A long accumulator like a carry-save adder.	Computing	2012	DBLP DOI BibTeX RDF
44	Anton Blad, Oscar Gustafsson	Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees.	ISCAS	2010	DBLP DOI BibTeX RDF
44	Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka	A low latency and low power dynamic Carry Save Adder.	ISCAS (2)	2004	DBLP BibTeX RDF
44	Patrik Larsson, Chris J. Nicol	Transition reduction in carry-save adder trees.	ISLPED	1996	DBLP DOI BibTeX RDF
44	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
39	Haridimos T. Vergos, Costas Efstathiou	Novel Modulo 2n + 1 Multipliers.	DSD	2006	DBLP DOI BibTeX RDF
32	Kamal Rajagopalan, Peter R. Sutton	A flexible multiplication unit for an FPGA logic block.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
32	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
31	Robert D. Kenney, Michael J. Schulte	High-Speed Multioperand Decimal Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic
31	Robert D. Kenney, Michael J. Schulte	Multioperand Decimal Addition.	ISVLSI	2004	DBLP DOI BibTeX RDF
31	Daeik D. Kim, Martin A. Brooke	A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
29	Yongjin Jeong, Wayne P. Burleson	VLSI array algorithms and architectures for RSA modular multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
27	Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong	Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m).	DELTA	2008	DBLP DOI BibTeX RDF	Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication
27	Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang	Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture.	DELTA	2004	DBLP DOI BibTeX RDF
27	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
27	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
24	Hee-Kwan Son, Sang-Geun Oh	Design and Implementation of Scalable Low-Power Montgomery Multiplier.	ICCD	2004	DBLP DOI BibTeX RDF
23	Kooroush Manochehri, Saadat Pourmozafari, Babak Sadeghiyan	Very Fast Multi Operand Addition Method by Bitwise Subtraction.	ITNG	2008	DBLP DOI BibTeX RDF	Fast multi addition, Bitwise subtraction, Recoding, Computer arithmetic, CSA
23	Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram	A Public-Key Cryptographic Processor for RSA and ECC.	ASAP	2004	DBLP DOI BibTeX RDF
23	Junhyung Um, Taewhan Kim	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	VLSI, arithmetic circuits, Carry-save-addition
23	Junhyung Um, Taewhan Kim, C. L. Liu 0001	Optimal allocation of carry-save-adders in arithmetic optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
18	Fan Mo, Robert K. Brayton	Placement based multiplier rewiring for cell-based designs.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Anup Hosangadi, Farzan Fallah, Ryan Kastner	Optimizing high speed arithmetic circuits using three-term extraction.	DATE	2006	DBLP DOI BibTeX RDF
18	Suryanarayana Tatapudi, José G. Delgado-Frias	A mesochronous pipeline scheme for high performance low power digital systems.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	redundant adders, digit sets, digit encodings, multiplier trees
18	Suryanarayana Tatapudi, José G. Delgado-Frias	A High Performance Hybrid Wave-Pipelined Multiplier.	ISVLSI	2005	DBLP DOI BibTeX RDF
18	Kooroush Manochehri, Saadat Pourmozafari	Modified Radix-2 Montgomery Modular Multiplication to Make It Faster and Simpler.	ITCC (1)	2005	DBLP DOI BibTeX RDF	Radix2, Exponentiation, Modular multiplication, Montgomery, CSA
18	Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.	FPL	2004	DBLP DOI BibTeX RDF
18	Junhyung Um, Taewhan Kim	Synthesis of arithmetic circuits considering layout effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic
18	Youngtae Kim, Taewhan Kim	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	Taewhan Kim, Junhyung Um	A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Taewhan Kim, William Jao, Steven W. K. Tjiang	Arithmetic Optimization Using Carry-Save-Adders.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band