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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 49 occurrences of 39 keywords
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Results
Found 46 publication records. Showing 46 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
119 | Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
Design of a radix-2m hybrid array multiplier using carry save adder format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 172-177, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hybrid multiplier, low power, carry save adder |
102 | Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar |
Minimum-adder integer multipliers using carry-save adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 709-712, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
84 | Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 243-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier |
66 | Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002 |
High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2006, 9th International Conference, Busan, Korea, November 30 - December 1, 2006, Proceedings, pp. 81-93, 2006, Springer, 3-540-49112-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder |
66 | Junhyung Um, Taewhan Kim |
Layout-aware synthesis of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 207-212, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
layout, high performance, carry-save-adder |
63 | Taewhan Kim, William Jao, Steven W. K. Tjiang |
Circuit optimization using carry-save-adder cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 974-984, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
55 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. |
Bit-level arithmetic optimization for carry-save additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 14-19, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Stamatis Vassiliadis, James Phillips, Bart Blaner |
Interlock Collapsing ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 825-839, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement |
47 | Daniel E. Atkins, Shauchi Ong |
Time-Component Complexity of Two Approaches to Multioperand Binary Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(12), pp. 918-926, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition |
44 | Melika Amiri, Massoud Dousti, Majid Mohammadi |
Design and implementation of carry-save adder using quantum-dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 80(2), pp. 1554-1567, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
44 | Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini |
An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(2), pp. 2150021:1-2150021:17, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
44 | Debashis De, Jadav Chandra Das |
Design of novel carry save adder using quantum dot-cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. ![In: J. Comput. Sci. 22, pp. 54-68, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
44 | Song Jia, Shigong Lyu, Xiayu Li, Li Liu, Yandong He |
Simplified carry save adder-based array multiplier scheme and circuits design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 43(9), pp. 1226-1234, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
44 | Stefan Siegel, Jürgen Wolff von Gudenberg |
A long accumulator like a carry-save adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 94(2-4), pp. 203-213, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
44 | Anton Blad, Oscar Gustafsson |
Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 181-184, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
44 | Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka |
A low latency and low power dynamic Carry Save Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 477-480, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
44 | Patrik Larsson, Chris J. Nicol |
Transition reduction in carry-save adder trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996, pp. 85-88, 1996, IEEE, 0-7803-3571-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
44 | A. Neslin Ismailoglu, Murat Askar |
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3259-3262, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Haridimos T. Vergos, Costas Efstathiou |
Novel Modulo 2n + 1 Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 168-175, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Kamal Rajagopalan, Peter R. Sutton |
A flexible multiplication unit for an FPGA logic block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 546-549, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Robert T. Grisamore, Earl E. Swartzlander Jr. |
Negative Save Sign Extension for Multi-term Adders and Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 1-11, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers |
31 | Robert D. Kenney, Michael J. Schulte |
High-Speed Multioperand Decimal Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 953-963, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic |
31 | Robert D. Kenney, Michael J. Schulte |
Multioperand Decimal Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 251-253, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Daeik D. Kim, Martin A. Brooke |
A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 1009-1012, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Yongjin Jeong, Wayne P. Burleson |
VLSI array algorithms and architectures for RSA modular multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 211-217, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong |
Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 458-461, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication |
27 | Zhi Ye, Ravi Kumar Satzoda, Udit Sharma, Naveen Nazimudeen, Chip-Hong Chang |
Performance Evaluation of Direct Form FIR Filter with Merged Arithmetic Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 407-409, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Peter Kornerup |
Reviewing 4-to-2 Adders for Multi-Operand Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 218-, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Chanyutt Arjhan, Raghvendra G. Deshmukh |
A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 127-132, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier |
24 | Hee-Kwan Son, Sang-Geun Oh |
Design and Implementation of Scalable Low-Power Montgomery Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 524-531, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Kooroush Manochehri, Saadat Pourmozafari, Babak Sadeghiyan |
Very Fast Multi Operand Addition Method by Bitwise Subtraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1240-1241, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Fast multi addition, Bitwise subtraction, Recoding, Computer arithmetic, CSA |
23 | Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram |
A Public-Key Cryptographic Processor for RSA and ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 98-110, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Junhyung Um, Taewhan Kim |
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(3), pp. 215-233, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
VLSI, arithmetic circuits, Carry-save-addition |
23 | Junhyung Um, Taewhan Kim, C. L. Liu 0001 |
Optimal allocation of carry-save-adders in arithmetic optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 410-413, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Fan Mo, Robert K. Brayton |
Placement based multiplier rewiring for cell-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 430-433, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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18 | Anup Hosangadi, Farzan Fallah, Ryan Kastner |
Optimizing high speed arithmetic circuits using three-term extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1294-1299, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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18 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A mesochronous pipeline scheme for high performance low power digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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18 | Peter Kornerup |
Reviewing 4-to-2 Adders for Multi-Operand Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 143-152, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
redundant adders, digit sets, digit encodings, multiplier trees |
18 | Suryanarayana Tatapudi, José G. Delgado-Frias |
A High Performance Hybrid Wave-Pipelined Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 282-283, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Kooroush Manochehri, Saadat Pourmozafari |
Modified Radix-2 Montgomery Modular Multiplication to Make It Faster and Simpler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 598-602, 2005, IEEE Computer Society, 0-7695-2315-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Radix2, Exponentiation, Modular multiplication, Montgomery, CSA |
18 | Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001 |
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 384-393, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Junhyung Um, Taewhan Kim |
Synthesis of arithmetic circuits considering layout effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1487-1503, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz |
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 171-190, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic |
18 | Youngtae Kim, Taewhan Kim |
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 622-628, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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18 | Taewhan Kim, Junhyung Um |
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 615-624, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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18 | Taewhan Kim, William Jao, Steven W. K. Tjiang |
Arithmetic Optimization Using Carry-Save-Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 433-438, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
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