Search results for "coarse-tuning"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
35	Georg Konstanznig, Andreas Springer, Robert Weigel	A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12µm standard CMOS.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
30	Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
27	Mahmoud Fawzy Wagdy, Brandon Casey Cabrales	A Novel Flash Fast-Locking Digital Phase-Locked Loop.	ITNG	2009	DBLP DOI BibTeX RDF	lock time, coarse-tuning, fine-tuning, CMOS, DPLL
25	Saeed Alzahrani, Salma Elabd, Waleed Khalil	A Wide Tuning Range Millimeter Wave CMOS LCVCO with Linearized Coarse Tuning Characteristics.	NEWCAS	2018	DBLP DOI BibTeX RDF
17	Atsushi Keyaki, Ribeka Keyaki	Coarse-Tuning for Ad-hoc Document Retrieval Using Pre-trained Language Models.	CoRR	2024	DBLP DOI BibTeX RDF
17	Yuanqing Huang, Yan Lu 0002, Franco Maloberti, Rui Paulo Martins	A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning.	ISCAS	2018	DBLP DOI BibTeX RDF
17	Gökhan Kayhan, Ali Ekber Ozdemir, Ilyas Eminoglu	Reviewing and designing pre-processing units for RBF networks: initial structure identification and coarse-tuning of free parameters.	Neural Comput. Appl.	2013	DBLP DOI BibTeX RDF
17	Yuanfeng Sun, Jian Qiao, Xueyi Yu, Woogeun Rhee, Byeong-Ha Park, Zhihua Wang 0001	A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
17	Jongsik Kim, Jaewook Shin, Seungsoo Kim, Hyunchol Shin	A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
17	Kang-Yoon Lee, Hyunchul Ku, Young Beom Kim	A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
15	Joonbae Park, Yido Koo, Wonchan Kim	A Semi-Digital Delay Locked Loop for Clock Skew Minimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
15	Richard Hsiao, Sheng-De Wang	Jelly: A Dynamic Hierarchical P2P Overlay Network with Load Balance and Locality.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF
15	Héctor Pomares, Ignacio Rojas, Jesús González 0001	New Methodology for Structure Identification of Fuzzy Controllers in Real Time.	IBERAMIA	2002	DBLP DOI BibTeX RDF
15	Ian Brynjolfson, Zeljko Zilic	A new PLL design for clock management applications.	ISCAS (4)	2001	DBLP DOI BibTeX RDF