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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 10 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
71 | Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano |
WWW based structuring of codesigns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 138-143, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
WWW based structuring, design by documentation, hypertext documents, World Wide Web, World Wide Web (WWW), hypermedia, systems analysis, codesigns, Mosaic, information networks, documentation generation, WWW browser |
70 | Marcel Pockrandt |
Model checking memory-related properties of hardware/software codesigns (Modelchecking Speicher-bezogener Eigenschaften für Hardware/Software Codesigns) ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2014 |
RDF |
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56 | Xu Guo 0001, Patrick Schaumont |
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 169-180, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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35 | Shail Dave, Tony Nowatzki, Aviral Shrivastava |
Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS (4) ![In: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023, pp. 87-107, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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35 | M. Mohamed Asan Basiri, Sandeep K. Shukla |
Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers, pp. 3-15, 2018, Springer, 978-981-13-5949-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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35 | Tim Todman, Peter Böhm, Wayne Luk |
Verification of streaming hardware and software codesigns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2012 International Conference on Field-Programmable Technology, FPT 2012, Seoul, Korea (South), December 10-12, 2012, pp. 147-150, 2012, IEEE, 978-1-4673-2846-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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35 | Peter Petrov, Alex Orailoglu |
Towards effective embedded processors in codesigns: customizable partitioned caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 79-84, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
reprogrammable customizations, embedded processors, data cache |
35 | Karam S. Chatha, Ranga Vemuri |
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Sixth International Workshop on Hardware/Software Codesign, CODES 1998, Seattle, Washington, USA, March 15-18, 1998, pp. 139-143, 1998, IEEE Computer Society, 0-8186-8442-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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35 | Karam S. Chatha, Ranga Vemuri |
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Workshop on Rapid System Prototyping ![In: Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), Leuven, Belgium, June 3-5, 1998, pp. 218-224, 1998, IEEE Computer Society, 0-8186-8479-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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28 | Peter Petrov, Alex Orailoglu |
A reprogrammable customization framework for efficient branch resolution in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 452-468, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Branch resolution, pipeline organization |
28 | Ian Page |
Constructing hardware-software systems from a single description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 12(1), pp. 87-107, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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