Results
Found 2 publication records. Showing 2 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
40 | Marco Platzner, Bernhard Rinner, Reinhold Weiss |
A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 311-318, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation |
22 | Jun-Cheol Lee, Tae-Oh Kim, Joo-Hyung Chae |
Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2023, Singapore, February 5-8, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2021-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #2 of 2 (100 per page; Change: )
|