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Found 56 publication records. Showing 56 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Venkatesh Akella, Ganesh Gopalakrishnan |
Specification and Validation of Control-Intensive IC's in hopCP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(6), pp. 405-423, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations |
44 | Daniel M. Lavery, Wen-mei W. Hwu |
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 126-137, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling |
19 | Edmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang |
High Level Verification of Control Intensive Systems Using Predicate Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 24-26 June 2003, Mont Saint-Michel, France, Proceedings, pp. 55-64, 2003, IEEE Computer Society, 0-7695-1923-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta |
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 261-266, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis |
13 | Jeffrey J. Cook, Craig B. Zilles |
Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 143-152, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Pohua P. Chang, Wen-mei W. Hwu |
Control flow optimization for supercomputer scalar processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 145-153, 1989, ACM, 0-89791-309-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
11 | Benoît Walter Denkinger, Miguel Peón Quirós, Mario Konijnenburg, David Atienza, Francky Catthoor |
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(9), pp. 2548-2560, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
11 | Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous |
Automatically batching control-intensive programs for modern accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLSys ![In: Proceedings of Machine Learning and Systems 2020, MLSys 2020, Austin, TX, USA, March 2-4, 2020, 2020, mlsys.org. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
11 | Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous |
Automatically Batching Control-Intensive Programs for Modern Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.11141, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
11 | Ali Mustafa Zaidi, David J. Greaves |
Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 9(2), pp. 14:1-14:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
11 | Leibo Liu, Junbin Wang, Jianfeng Zhu 0001, Chenchen Deng, Shouyi Yin, Shaojun Wei |
TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 27(7), pp. 2143-2154, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
11 | Jianfeng Zhu 0001, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei |
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(9), pp. 1700-1709, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
11 | Ali Mustafa Zaidi, David J. Greaves |
A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014, pp. 122-131, 2014, IEEE Computer Society, 978-0-7695-5208-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
11 | Marc-André Daigneault, Jean-Pierre David |
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013, pp. 274-275, 2013, ACM, 978-1-4503-1887-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Kyuseung Han, Kiyoung Choi, Jongeun Lee |
Compiling control-intensive loops for CGRAs with state-based full predication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 1579-1582, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Michael F. Dossis |
Formal ESL Synthesis for Control-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adv. Softw. Eng. ![In: Adv. Softw. Eng. 2012, pp. 156907:1-156907:30, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
11 | Michael F. Dossis |
Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece, pp. 98-103, 2010, IEEE Computer Society, 978-0-7695-4076-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Ganghee Lee, Kyungwook Chang, Kiyoung Choi |
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings, pp. 1-4, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Séverine Sentilles, Aneta Vulgarakis, Tomás Bures, Jan Carlson, Ivica Crnkovic |
A Component Model for Control-Intensive Distributed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBSE ![In: Component-Based Software Engineering, 11th International Symposium, CBSE 2008, Karlsruhe, Germany, October 14-17, 2008. Proceedings, pp. 310-317, 2008, Springer, 978-3-540-87890-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet |
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 177-182, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Chun Che Fung, Jiabin Li, Douglas G. Myers |
Evaluation of an Efficient Parallel Object Oriented Platform (EPOOP) for Control Intensive Intelligent Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMLC ![In: Advances in Machine Learning and Cybernetics, 4th International Conference, ICMLC 2005, Guangzhou, China, August 18-21, 2005, Revised Selected Papers, pp. 889-897, 2005, Springer, 3-540-33584-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau |
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10270-10275, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Claudia Blank |
Property verification of mixed data and control intensive designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2003 |
RDF |
|
11 | Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau |
Speculation Techniques for High Level Synthesis of Control Intensive Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 269-272, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Daniel M. Lavery |
Modulo Scheduling for Control-Intensive General-Purpose Programs ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1997 |
RDF |
|
10 | Jinwen Xi, Peixin Zhong |
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 502-504, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Simin Nadjm-Tehrani, Ove Åkerlund |
Combining Theorem Proving and Continuous Models in Synchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Formal Methods ![In: FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume II, pp. 1384-1399, 1999, Springer, 3-540-66588-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade |
Register Sharing Verification During Data-Path Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCTA ![In: 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India, pp. 135-140, 2007, IEEE Computer Society, 978-0-7695-2770-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Youngsoo Kim, Suleyman Sair |
Designing real-time H.264 decoders with dataflow architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 291-296, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
WaveScalar, H.264, dataflow architecture |
9 | Oleg Maslennikov, Juri Shevtshenko, Anatoli Sergyienko |
Configurable Microcontroller Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland, pp. 47-49, 2002, IEEE Computer Society, 0-7695-1730-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Yen-Kuang Chen, Sun-Yuan Kung |
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 20(1-2), pp. 181-204, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Wen-mei W. Hwu, Yale N. Patt |
Exploiting horizontal and vertical concurrency via the HPSm microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 154-161, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
8 | Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank |
Branch-mispredict level parallelism (BLP) for control independence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 62-73, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Hans M. Jacobson, Ganesh Gopalakrishnan |
Asynchronous Microengines for Efficient High-level Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 201-218, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous circuits, microprogramming, self-timing |
7 | Peter Petrov, Alex Orailoglu |
A reprogrammable customization framework for efficient branch resolution in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 452-468, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Branch resolution, pipeline organization |
7 | John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu |
Field-testing IMPACT EPIC research results in Itanium 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 26-39, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
6 | Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer |
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China, pp. 1874-1877, 2007, IEEE Computer Society, 1-4244-1017-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
6 | Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen |
Efficient detection and exploitation of infeasible paths for software timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 358-363, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
infeasible path detection, WCET analysis |
6 | Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally |
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, November 12-18, 2005, Seattle, WA, USA, CD-Rom, pp. 29, 2005, IEEE Computer Society, 1-59593-061-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
6 | Michael Sung, Ronny Krashinsky, Krste Asanovic |
Multithreading decoupled architectures for complexity-effective general purpose computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(5), pp. 56-61, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Brian L. Deitrich, Wen-mei W. Hwu |
Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 70-79, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu |
An asymmetric distributed shared memory model for heterogeneous parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 347-358, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asymmetric distributed shared memory, data-centric programming models, heterogeneous systems |
5 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh |
Retargetable Code Optimization for Predicated Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1492-1497, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Víctor A. Braberman, Nicolas Kicillof, Alfredo Olivero |
A Scenario-Matching Approach to the Description and Model Checking of Real-Time Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 31(12), pp. 1028-1041, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scenario-based verification, model checking, formal methods, Requirements/specifications |
5 | Edmund M. Clarke, Anubhav Gupta 0001, Himanshu Jain, Helmut Veith |
Model Checking: Back and Forth between Hardware and Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VSTTE ![In: Verified Software: Theories, Tools, Experiments, First IFIP TC 2/WG 2.3 Conference, VSTTE 2005, Zurich, Switzerland, October 10-13, 2005, Revised Selected Papers and Discussions, pp. 251-255, 2005, Springer, 978-3-540-69147-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
5 | Roope Kaivola |
Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 17th International Conference, CAV 2005, Edinburgh, Scotland, UK, July 6-10, 2005, Proceedings, pp. 170-184, 2005, Springer, 3-540-27231-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
5 | Michael Dupré, Nathalie Drach, Olivier Temam |
VHC: Quickly Building an Optimizer for Complex Embedded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 53-64, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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5 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Cosimulation-based power estimation for system-on-chip design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(3), pp. 253-266, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Gordon J. Brebner |
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 35-44, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Robert P. Kurshan |
Model Checking and Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SARA ![In: Abstraction, Reformulation and Approximation, 5th International Symposium, SARA 2002, Kananaskis, Alberta, Canada, August 2-4, 2002, Proceedings, pp. 1-17, 2002, Springer, 3-540-43941-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Efficient Power Co-Estimation Techniques for System-on-Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 27-34, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
5 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto |
RT-level TPG Exploiting High-Level Synthesis Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 341-353, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
5 | D. K. Arvind 0001, Salvador Sotelo-Salazar |
Scheduling Instructions with Uncertain Latencies in Asynchronous Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 771-778, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
5 | Sebastian Schmidt 0003 |
Global Instruction Scheduling - a Practical Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 815-818, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Ramin Hojati, Robert K. Brayton |
Automatic Datapath Abstraction In Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 98-113, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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5 | Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu |
A Comparison of Full and Partial Predicated Execution Support for ILP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 138-150, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
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