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Searching for phrase control-intensive (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1987-2000 (15) 2001-2005 (20) 2006-2014 (15) 2015-2023 (6)
Publication types (Num. hits)
article(12) inproceedings(42) phdthesis(2)
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The graphs summarize 30 occurrences of 29 keywords

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Found 56 publication records. Showing 56 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
44Venkatesh Akella, Ganesh Gopalakrishnan Specification and Validation of Control-Intensive IC's in hopCP. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations
44Daniel M. Lavery, Wen-mei W. Hwu Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. Search on Bibsonomy MICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling
19Edmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang High Level Verification of Control Intensive Systems Using Predicate Abstraction. Search on Bibsonomy MEMOCODE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
17Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis
13Jeffrey J. Cook, Craig B. Zilles Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. Search on Bibsonomy ISPASS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
12Pohua P. Chang, Wen-mei W. Hwu Control flow optimization for supercomputer scalar processing. Search on Bibsonomy ICS The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
11Benoît Walter Denkinger, Miguel Peón Quirós, Mario Konijnenburg, David Atienza, Francky Catthoor Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
11Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous Automatically batching control-intensive programs for modern accelerators. Search on Bibsonomy MLSys The full citation details ... 2020 DBLP  BibTeX  RDF
11Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous Automatically Batching Control-Intensive Programs for Modern Accelerators. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
11Ali Mustafa Zaidi, David J. Greaves Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
11Leibo Liu, Junbin Wang, Jianfeng Zhu 0001, Chenchen Deng, Shouyi Yin, Shaojun Wei TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
11Jianfeng Zhu 0001, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
11Ali Mustafa Zaidi, David J. Greaves A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. Search on Bibsonomy IPDPS Workshops The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
11Marc-André Daigneault, Jean-Pierre David Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). Search on Bibsonomy FPGA The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
11Kyuseung Han, Kiyoung Choi, Jongeun Lee Compiling control-intensive loops for CGRAs with state-based full predication. Search on Bibsonomy DATE The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
11Michael F. Dossis Formal ESL Synthesis for Control-Intensive Applications. Search on Bibsonomy Adv. Softw. Eng. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
11Michael F. Dossis Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs. Search on Bibsonomy ISVLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
11Ganghee Lee, Kyungwook Chang, Kiyoung Choi Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. Search on Bibsonomy IPDPS Workshops The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
11Séverine Sentilles, Aneta Vulgarakis, Tomás Bures, Jan Carlson, Ivica Crnkovic A Component Model for Control-Intensive Distributed Embedded Systems. Search on Bibsonomy CBSE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
11C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
11Chun Che Fung, Jiabin Li, Douglas G. Myers Evaluation of an Efficient Parallel Object Oriented Platform (EPOOP) for Control Intensive Intelligent Applications. Search on Bibsonomy ICMLC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
11Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
11Claudia Blank Property verification of mixed data and control intensive designs. Search on Bibsonomy 2003   RDF
11Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau Speculation Techniques for High Level Synthesis of Control Intensive Designs. Search on Bibsonomy DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
11Daniel M. Lavery Modulo Scheduling for Control-Intensive General-Purpose Programs Search on Bibsonomy 1997   RDF
10Jinwen Xi, Peixin Zhong Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
10Simin Nadjm-Tehrani, Ove Åkerlund Combining Theorem Proving and Continuous Models in Synchronous Design. Search on Bibsonomy World Congress on Formal Methods The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
9Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade Register Sharing Verification During Data-Path Synthesis. Search on Bibsonomy ICCTA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
9Youngsoo Kim, Suleyman Sair Designing real-time H.264 decoders with dataflow architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF WaveScalar, H.264, dataflow architecture
9Oleg Maslennikov, Juri Shevtshenko, Anatoli Sergyienko Configurable Microcontroller Array. Search on Bibsonomy PARELEC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
9Yen-Kuang Chen, Sun-Yuan Kung Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
9Wen-mei W. Hwu, Yale N. Patt Exploiting horizontal and vertical concurrency via the HPSm microprocessor. Search on Bibsonomy MICRO The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
8Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank Branch-mispredict level parallelism (BLP) for control independence. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
8Hans M. Jacobson, Ganesh Gopalakrishnan Asynchronous Microengines for Efficient High-level Control. Search on Bibsonomy ARVLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF asynchronous circuits, microprogramming, self-timing
7Peter Petrov, Alex Orailoglu A reprogrammable customization framework for efficient branch resolution in embedded processors. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Branch resolution, pipeline organization
7John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu Field-testing IMPACT EPIC research results in Itanium 2. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
6Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. Search on Bibsonomy ICME The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
6Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen Efficient detection and exploitation of infeasible paths for software timing analysis. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF infeasible path detection, WCET analysis
6Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. Search on Bibsonomy SC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
6Michael Sung, Ronny Krashinsky, Krste Asanovic Multithreading decoupled architectures for complexity-effective general purpose computing. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
6Brian L. Deitrich, Wen-mei W. Hwu Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. Search on Bibsonomy MICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
5Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu An asymmetric distributed shared memory model for heterogeneous parallel systems. Search on Bibsonomy ASPLOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asymmetric distributed shared memory, data-centric programming models, heterogeneous systems
5Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh Retargetable Code Optimization for Predicated Execution. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
5Víctor A. Braberman, Nicolas Kicillof, Alfredo Olivero A Scenario-Matching Approach to the Description and Model Checking of Real-Time Properties. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scenario-based verification, model checking, formal methods, Requirements/specifications
5Edmund M. Clarke, Anubhav Gupta 0001, Himanshu Jain, Helmut Veith Model Checking: Back and Forth between Hardware and Software. Search on Bibsonomy VSTTE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
5Roope Kaivola Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants. Search on Bibsonomy CAV The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
5Michael Dupré, Nathalie Drach, Olivier Temam VHC: Quickly Building an Optimizer for Complex Embedded Architectures. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
5Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno Cosimulation-based power estimation for system-on-chip design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
5Gordon J. Brebner Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. Search on Bibsonomy FCCM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
5Robert P. Kurshan Model Checking and Abstraction. Search on Bibsonomy SARA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
5Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno Efficient Power Co-Estimation Techniques for System-on-Chip Design. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
5Silvia Chiusano, Fulvio Corno, Paolo Prinetto RT-level TPG Exploiting High-Level Synthesis Information. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
5D. K. Arvind 0001, Salvador Sotelo-Salazar Scheduling Instructions with Uncertain Latencies in Asynchronous Architectures. Search on Bibsonomy Euro-Par The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
5Sebastian Schmidt 0003 Global Instruction Scheduling - a Practical Approach. Search on Bibsonomy Euro-Par, Vol. II The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
5Ramin Hojati, Robert K. Brayton Automatic Datapath Abstraction In Hardware Systems. Search on Bibsonomy CAV The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
5Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu A Comparison of Full and Partial Predicated Execution Support for ILP Processors. Search on Bibsonomy ISCA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
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