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Found 56 publication records. Showing 56 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Venkatesh Akella, Ganesh Gopalakrishnan |
Specification and Validation of Control-Intensive IC's in hopCP. |
IEEE Trans. Software Eng. |
1994 |
DBLP DOI BibTeX RDF |
control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations |
44 | Daniel M. Lavery, Wen-mei W. Hwu |
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. |
MICRO |
1996 |
DBLP DOI BibTeX RDF |
control-intensive, modulo variable expansion, instruction-level parallelism, software pipelining, speculation, modulo scheduling |
19 | Edmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang |
High Level Verification of Control Intensive Systems Using Predicate Abstraction. |
MEMOCODE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta |
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis |
13 | Jeffrey J. Cook, Craig B. Zilles |
Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Pohua P. Chang, Wen-mei W. Hwu |
Control flow optimization for supercomputer scalar processing. |
ICS |
1989 |
DBLP DOI BibTeX RDF |
|
11 | Benoît Walter Denkinger, Miguel Peón Quirós, Mario Konijnenburg, David Atienza, Francky Catthoor |
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems. |
IEEE Trans. Computers |
2023 |
DBLP DOI BibTeX RDF |
|
11 | Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous |
Automatically batching control-intensive programs for modern accelerators. |
MLSys |
2020 |
DBLP BibTeX RDF |
|
11 | Alexey Radul, Brian Patton, Dougal Maclaurin, Matthew D. Hoffman, Rif A. Saurous |
Automatically Batching Control-Intensive Programs for Modern Accelerators. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
11 | Ali Mustafa Zaidi, David J. Greaves |
Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. |
ACM Trans. Reconfigurable Technol. Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
11 | Leibo Liu, Junbin Wang, Jianfeng Zhu 0001, Chenchen Deng, Shouyi Yin, Shaojun Wei |
TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. |
IEEE Trans. Parallel Distributed Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
11 | Jianfeng Zhu 0001, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei |
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. |
IEEE Trans. Very Large Scale Integr. Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
11 | Ali Mustafa Zaidi, David J. Greaves |
A New Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. |
IPDPS Workshops |
2014 |
DBLP DOI BibTeX RDF |
|
11 | Marc-André Daigneault, Jean-Pierre David |
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). |
FPGA |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Kyuseung Han, Kiyoung Choi, Jongeun Lee |
Compiling control-intensive loops for CGRAs with state-based full predication. |
DATE |
2013 |
DBLP DOI BibTeX RDF |
|
11 | Michael F. Dossis |
Formal ESL Synthesis for Control-Intensive Applications. |
Adv. Softw. Eng. |
2012 |
DBLP DOI BibTeX RDF |
|
11 | Michael F. Dossis |
Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Ganghee Lee, Kyungwook Chang, Kiyoung Choi |
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. |
IPDPS Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Séverine Sentilles, Aneta Vulgarakis, Tomás Bures, Jan Carlson, Ivica Crnkovic |
A Component Model for Control-Intensive Distributed Embedded Systems. |
CBSE |
2008 |
DBLP DOI BibTeX RDF |
|
11 | C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet |
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Chun Che Fung, Jiabin Li, Douglas G. Myers |
Evaluation of an Efficient Parallel Object Oriented Platform (EPOOP) for Control Intensive Intelligent Applications. |
ICMLC |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau |
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Claudia Blank |
Property verification of mixed data and control intensive designs. |
|
2003 |
RDF |
|
11 | Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau |
Speculation Techniques for High Level Synthesis of Control Intensive Designs. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Daniel M. Lavery |
Modulo Scheduling for Control-Intensive General-Purpose Programs |
|
1997 |
RDF |
|
10 | Jinwen Xi, Peixin Zhong |
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Simin Nadjm-Tehrani, Ove Åkerlund |
Combining Theorem Proving and Continuous Models in Synchronous Design. |
World Congress on Formal Methods |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade |
Register Sharing Verification During Data-Path Synthesis. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Youngsoo Kim, Suleyman Sair |
Designing real-time H.264 decoders with dataflow architectures. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
WaveScalar, H.264, dataflow architecture |
9 | Oleg Maslennikov, Juri Shevtshenko, Anatoli Sergyienko |
Configurable Microcontroller Array. |
PARELEC |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Yen-Kuang Chen, Sun-Yuan Kung |
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation. |
J. VLSI Signal Process. |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Wen-mei W. Hwu, Yale N. Patt |
Exploiting horizontal and vertical concurrency via the HPSm microprocessor. |
MICRO |
1987 |
DBLP DOI BibTeX RDF |
|
8 | Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank |
Branch-mispredict level parallelism (BLP) for control independence. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Hans M. Jacobson, Ganesh Gopalakrishnan |
Asynchronous Microengines for Efficient High-level Control. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
asynchronous circuits, microprogramming, self-timing |
7 | Peter Petrov, Alex Orailoglu |
A reprogrammable customization framework for efficient branch resolution in embedded processors. |
ACM Trans. Embed. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Branch resolution, pipeline organization |
7 | John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu |
Field-testing IMPACT EPIC research results in Itanium 2. |
ISCA |
2004 |
DBLP DOI BibTeX RDF |
|
6 | Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer |
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
6 | Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen |
Efficient detection and exploitation of infeasible paths for software timing analysis. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
infeasible path detection, WCET analysis |
6 | Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally |
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. |
SC |
2005 |
DBLP DOI BibTeX RDF |
|
6 | Michael Sung, Ronny Krashinsky, Krste Asanovic |
Multithreading decoupled architectures for complexity-effective general purpose computing. |
SIGARCH Comput. Archit. News |
2001 |
DBLP DOI BibTeX RDF |
|
6 | Brian L. Deitrich, Wen-mei W. Hwu |
Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. |
MICRO |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu |
An asymmetric distributed shared memory model for heterogeneous parallel systems. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
asymmetric distributed shared memory, data-centric programming models, heterogeneous systems |
5 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh |
Retargetable Code Optimization for Predicated Execution. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Víctor A. Braberman, Nicolas Kicillof, Alfredo Olivero |
A Scenario-Matching Approach to the Description and Model Checking of Real-Time Properties. |
IEEE Trans. Software Eng. |
2005 |
DBLP DOI BibTeX RDF |
scenario-based verification, model checking, formal methods, Requirements/specifications |
5 | Edmund M. Clarke, Anubhav Gupta 0001, Himanshu Jain, Helmut Veith |
Model Checking: Back and Forth between Hardware and Software. |
VSTTE |
2005 |
DBLP DOI BibTeX RDF |
|
5 | Roope Kaivola |
Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants. |
CAV |
2005 |
DBLP DOI BibTeX RDF |
|
5 | Michael Dupré, Nathalie Drach, Olivier Temam |
VHC: Quickly Building an Optimizer for Complex Embedded Architectures. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
5 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Cosimulation-based power estimation for system-on-chip design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Gordon J. Brebner |
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. |
FCCM |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Robert P. Kurshan |
Model Checking and Abstraction. |
SARA |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Efficient Power Co-Estimation Techniques for System-on-Chip Design. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
5 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto |
RT-level TPG Exploiting High-Level Synthesis Information. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
5 | D. K. Arvind 0001, Salvador Sotelo-Salazar |
Scheduling Instructions with Uncertain Latencies in Asynchronous Architectures. |
Euro-Par |
1997 |
DBLP DOI BibTeX RDF |
|
5 | Sebastian Schmidt 0003 |
Global Instruction Scheduling - a Practical Approach. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
5 | Ramin Hojati, Robert K. Brayton |
Automatic Datapath Abstraction In Hardware Systems. |
CAV |
1995 |
DBLP DOI BibTeX RDF |
|
5 | Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu |
A Comparison of Full and Partial Predicated Execution Support for ILP Processors. |
ISCA |
1995 |
DBLP DOI BibTeX RDF |
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