Search results for "custom"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang	A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.	DATE	2003	DBLP DOI BibTeX RDF
58	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Custom-instruction synthesis for extensible-processor platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
57	Laurence Bull, Peter Stañski, David Squire	Content extraction signatures using XML digital signatures and custom transforms on-demand.	WWW	2003	DBLP DOI BibTeX RDF	Net framework XML signature API, XML signature custom transforms, content extraction signatures, XML signatures, dynamic signature verification
52	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
52	Vasian Cepa, Mira Mezini	Declaring and Enforcing Dependencies Between .NET Custom Attributes.	GPCE	2004	DBLP DOI BibTeX RDF
52	Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll	A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays.	ASAP	1997	DBLP DOI BibTeX RDF
52	Andrew Chang 0001, William J. Dally	Explaining the gap between ASIC and custom power: a custom perspective.	DAC	2005	DBLP DOI BibTeX RDF	custom circuits, normalized metrics, low power, energy efficiency, ASIC, EDA, technology scaling
51	Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye	Custom is from Venus and synthesis from Mars.	DAC	2008	DBLP DOI BibTeX RDF	IC synthesis techniques, custom IC design, VLSI design
50	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design.	DATE	1998	DBLP DOI BibTeX RDF	Gallium Arsenide automated layout generation system, GaAs VLSI design, power supply and ground distribution model, full-custom cell layout style, full-custom layouts of very high speed circuits, cell library builder, random logic macrocell generator, iterative logic array generator
46	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
46	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
46	Bruce R. Childers, Jack W. Davidson	Custom Wide Counterflow Pipelines for High-Performance Embedded Applications.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Counterflow pipelines, automatic architectural synthesis, application-specific processors
46	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
45	Naren Datha, Tanuja Joshi, Joseph Joy, Vibhuti S. Sengar	Custom local search.	GIS	2009	DBLP DOI BibTeX RDF	custom location search, robust parsing, geocoding
45	Tao Li 0008, Zhigang Sun, Wu Jigang, Xicheng Lu	Fast enumeration of maximal valid subgraphs for custom-instruction identification.	CASES	2009	DBLP DOI BibTeX RDF	ISE identification, custom processors, maximal subgraph
45	Emre Özer 0001, Andy Nisbet, David Gregg	A stochastic bitwidth estimation technique for compact and low-power custom processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Bit-width analysis, custom hardware, FPGA, statistical estimation, extreme value theory
45	Hai Lin 0004, Yunsi Fei	Utilizing custom registers in application-specific instruction set processors for register spills elimination.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	custom register, ASIP, register file
45	Laurence Bull, David McG. Squire	XML Signature Extensibility Using Custom Transforms.	WISE	2004	DBLP DOI BibTeX RDF	XML Signature Custom Transforms, XML Signatures
45	José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos	FAFNER-Accelerating Nesting Problems with FPGAs.	FCCM	1999	DBLP DOI BibTeX RDF	Custom computing, nesting problems, FPGAs
45	Neil W. Bergmann, Yuk Ying Chung	Video Compression on FPGA-Based Custom Computers.	ICIP (1)	1997	DBLP DOI BibTeX RDF	FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed
45	Jason L. Dedrick, Sean Xin Xu, Kevin Zhu	Information Technology and the Number of Suppliers in a Supply Chain: Is There a Relationship?	HICSS	2008	DBLP DOI BibTeX RDF	supply chain relationships, number of suppliers, electronic procurement, custom goods, systems integration, transaction costs economics
41	Nabeel Shirazi, Al Walters, Peter M. Athanas	Quantitative analysis of floating point arithmetic on FPGA based custom computing machines.	FCCM	1995	DBLP DOI BibTeX RDF
41	Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider	Teramac-configurable custom computing.	FCCM	1995	DBLP DOI BibTeX RDF
41	Tao Li 0008, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu	Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
41	Liana Razmerita, Niels Bjørn-Andersen	Towards Ubiquitous e-Custom Services.	Web Intelligence	2007	DBLP DOI BibTeX RDF
41	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
40	Elizeu Santos-Neto, Samer Al-Kiswany, Nazareno Andrade, Sathish Gopalakrishnan, Matei Ripeanu	enabling cross-layer optimizations in storage systems with custom metadata.	HPDC	2008	DBLP DOI BibTeX RDF	custom metadata, cross-layer optimization, distributed storage systems
40	David G. Chinnery, Kurt Keutzer	Closing the power gap between ASIC and custom: an ASIC perspective.	DAC	2005	DBLP DOI BibTeX RDF	power, energy, custom, ASIC, comparison, standard cell
40	Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz	Coarse-Grain Pipelining on Multiple FPGA Architectures.	FCCM	2002	DBLP DOI BibTeX RDF	Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques
40	Li-C. Wang, Magdy S. Abadir	On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	custom circuits, high level circuit extraction, ATPG, DFT, time-to-market
40	David G. Chinnery, Kurt Keutzer	Closing the gap between ASIC and custom: an ASIC perspective.	DAC	2000	DBLP DOI BibTeX RDF	custom, ASIC, comparison, clock frequency, clock speed
40	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
40	Eric Persoon	A Pipelined Image Analysis System Using Custom Integrated Circuits.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	pipelined image analysis system, custom integrated circuits, iconic image-processing, mask generation, programmable image delay, subsample filtering, computer vision, computerised picture processing, pipeline processing, shape recognition, digital integrated circuits, computer vision system
35	Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk	CHIPS: Custom Hardware Instruction Processor Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
35	Pan Yu, Tulika Mitra	Disjoint Pattern Enumeration for Custom Instructions Identification.	FPL	2007	DBLP DOI BibTeX RDF
35	Bita Gorjiara, Daniel D. Gajski	Custom Processor Design Using NISC: A Case-Study on DCT algorithm.	ESTIMedia	2005	DBLP DOI BibTeX RDF
35	Antonio Blotti, Roberto Saletti	Ultralow-power adiabatic circuit semi-custom design.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
35	Chris Gniady, Babak Falsafi	Speculative Sequential Consistency with Little Custom Storage.	IEEE PACT	2002	DBLP DOI BibTeX RDF
35	Emery D. Berger, Benjamin G. Zorn, Kathryn S. McKinley	Reconsidering custom memory allocation.	OOPSLA	2002	DBLP DOI BibTeX RDF
35	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
34	Huynh Phung Huynh, Tulika Mitra	Runtime Adaptive Extensible Embedded Processors - A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
34	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Scalable Synthesis Methodology for Application-Specific Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim	Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Coherence controller, protocol processor, multiprocessor, shared memory
34	Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott	Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.	ISCA	1997	DBLP DOI BibTeX RDF
34	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
34	João Miguel Ferro, Fernando J. Velez	Routing in a Custom-Made IEEE 802.11E Simulator.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	IEEE 802.11E Simulator, Custom-Made, multi-hop environment, Routing, network simulation
34	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham	A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.	Formal Methods Syst. Des.	2005	DBLP DOI BibTeX RDF	efficient memory models, embedded memory verification, custom circuit verification, equivalence checking, symbolic trajectory evaluation
34	GuangWei Zou, Xiang Liu	An Efficient Approach to Custom Instruction Set Generation.	RTCSA	2005	DBLP DOI BibTeX RDF	Major Block, Profiling, Hardware Acceleration, ASIPs, Custom Instruction
34	Javier Ramírez 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García 0001, Antonio Lloris-Ruíz	Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	RNS arithmetic, custom integrated circuit, field-programmable logic devices, discrete wavelet transform
34	Barbara Cannas, Gianni Celli, Alessandra Fanni, Fabrizio Pilo	Automated Recurrent Neural Network Design of a Neural Controller in a Custom Power Device.	J. Intell. Robotic Syst.	2001	DBLP DOI BibTeX RDF	custom power protection device, universal Tabu Search, recurrent neural networks, neural controller
34	Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides	Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation.	FCCM	1998	DBLP DOI BibTeX RDF	FPGA, Architecture, Custom, Golomb Ruler
34	Venkat Thanvantri, Sartaj Sahni	Optimal folding of standard and custom cells.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	custom cell folding, standard cell folding, layout area
33	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani	An architecture framework for an adaptive extensible processor.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Reconfigurable functional unit, Profiling, Temporal partitioning, Custom instruction, Extensible processor, Similarity detection
33	Guy G. Lemieux, Tarek A. El-Ghazawi	Designing with extreme parallelism.	FPGA	2008	DBLP DOI BibTeX RDF	custom compute engine, high-level electronic design, FPGA, parallel processing, reconfigurable computing, hardware description language
33	Beng-Hong Lim, Philip Heidelberger, Pratap Pattnaik, Marc Snir	Message Proxies for Efficient, Protected Communication on SMP Clusters.	HPCA	1997	DBLP DOI BibTeX RDF	message proxies, protected communication, custom hardware, IBM Model G30 SMPs, cache-miss latency, cache-update mechanism, performance model, multiprocessing systems, symmetric multiprocessor clusters
30	Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong	Map-reduce as a Programming Model for Custom Computing Machines.	FCCM	2008	DBLP DOI BibTeX RDF
30	Christian Plessl, Marco Platzner	Custom Computing Machines for the Set Covering Problem.	FCCM	2002	DBLP DOI BibTeX RDF
30	Mark J. Boyd, Tracy Larrabee	A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems.	FCCM	2000	DBLP DOI BibTeX RDF
30	W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider	Defect tolerance on the Teramac custom computer.	FCCM	1997	DBLP DOI BibTeX RDF
30	Neil W. Bergmann, Yuk Ying Chung, Bernard K. Gunther	Efficient implementation of the DCT on custom computers.	FCCM	1997	DBLP DOI BibTeX RDF
30	Glenn H. Chapman, Benoit Dufort	Laser defect correction applications to FPGA based custom computers.	FCCM	1997	DBLP DOI BibTeX RDF
30	Kazuhiro Hayashi, Toshiaki Miyazaki, Kazuhiro Shirakawa, Kazuhisa Yamada, Naohisa Ohta	Reconfigurable real-time signal transport system using custom FPGAs.	FCCM	1995	DBLP DOI BibTeX RDF
30	Wayne Luk	A declarative approach to incremental custom computing.	FCCM	1995	DBLP DOI BibTeX RDF
29	Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin	Reconfigurable custom floating-point instructions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	emips, reconfigurable, extension, floating-point, partial reconfiguration
29	Siddharth Garg, Diana Marculescu, Radu Marculescu	Custom feedback control: enabling truly scalable on-chip power management for MPSoCs.	ISLPED	2010	DBLP DOI BibTeX RDF	distributed control, dynamic voltage/frequency scaling
29	Hai Lin 0004, Yunsi Fei	Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives.	ISLPED	2010	DBLP DOI BibTeX RDF	asips, multi-objective design
29	Vinayak Honkote, Baris Taskin	PEEC based parasitic modeling for power analysis on custom rotary rings.	ISLPED	2010	DBLP DOI BibTeX RDF	resonant clocking, simulation, modeling, interconnect
29	Vinayak Honkote, Baris Taskin	Custom rotary clock router.	ICCD	2008	DBLP DOI BibTeX RDF
29	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song 0002, Satoshi Goto	HyMacs: hybrid memory access optimization based on custom-instruction scheduling.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asip, cad algorithm, hardware/software co-design
29	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.	VLSI Design	2008	DBLP DOI BibTeX RDF
29	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi	Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.	DATE	2007	DBLP DOI BibTeX RDF
29	Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung	A Hybrid Memory Sub-system for Video Coding Applications.	FCCM	2007	DBLP DOI BibTeX RDF
29	Alin Jula, Lawrence Rauchwerger	Custom Memory Allocation for Free.	LCPC	2006	DBLP DOI BibTeX RDF
29	Lorenz Huelsbergen	Fast evolution of custom machine representations.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
29	Pan Yu, Tulika Mitra	Satisfying real-time constraints with custom instructions.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	real-time systems, execution time, instruction-set extensions, worst-case, customizable processors
29	Krishnan Srinivasan, Karam S. Chatha	ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
29	Shannon Xu, Thomas R. Dean	Transforming Embedded Java Code into Custom Tags.	SCAM	2005	DBLP DOI BibTeX RDF
29	Shawn Phillips, Scott Hauck	Automating the Layout of Reconfigurable Subsystems Using Circuit Generators.	FCCM	2005	DBLP DOI BibTeX RDF
29	Rick Mugridge	Test Driving Custom Fit Fixtures.	XP	2004	DBLP DOI BibTeX RDF	Customer testing, tdd, it
29	Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer	FPGA Custom DSP for ECG Signal Analysis and Compression.	FPL	2004	DBLP DOI BibTeX RDF
29	Dan Kuyper, Hesham H. Ali, Amr M. Mohamed, Steven H. Hinrichs	Identification of Mycobacterium Species Using Curated Custom Databases.	IPDPS	2004	DBLP DOI BibTeX RDF
29	Pan Yu, Tulika Mitra	Scalable custom instructions identification for instruction-set extensible processors.	CASES	2004	DBLP DOI BibTeX RDF	subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
29	Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman	A semi-custom voltage-island technique and its application to high-speed serial links.	ISLPED	2003	DBLP DOI BibTeX RDF	island, voltage, communications, low power, links, serial
29	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers	Field-Programmable Custom Computing Machines - A Taxonomy -.	FPL	2002	DBLP DOI BibTeX RDF
29	Paul P. Polanski, Robert B. Johnston	International Custom as a Source of Law in Global Electronic Commerce.	HICSS	2002	DBLP DOI BibTeX RDF
29	Bruce R. Childers, Jack W. Davidson	Custom Wide Counterflow Pipelines for High-Performance Embedded Applications.	IEEE PACT	2000	DBLP DOI BibTeX RDF
29	Andrew A. Duncan, David C. Hendry, Peter Gray	An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems.	FCCM	1998	DBLP DOI BibTeX RDF
29	James B. Peterson, Peter M. Athanas	High-speed 2-D convolution with a custom computing machine.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
29	R. Larry Dooley, G. Heimke, Ajit Dingankar, E. Berg, E. Kimbrough	Automated Design and Analysis System for Design of Custom Orthopedic Implants.	IEA/AIE (Vol. 1)	1988	DBLP DOI BibTeX RDF	LISP
28	Robert Law	Using student blogs for documentation in software development projects.	ITiCSE	2011	DBLP DOI BibTeX RDF
28	Matthew Canton	The presence table: a reactive surface for ambient connection.	TEI	2011	DBLP DOI BibTeX RDF
28	Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad Mukarram Bin Tariq, Nick Feamster	SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware.	SIGCOMM	2010	DBLP DOI BibTeX RDF	network virtualization, NetFPGA
28	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Application-specific heterogeneous multiprocessor synthesis using extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Trieu C. Chieu, Florian Pinel, Jih-Shyr Yih	Unified Commerce Server Architecture for Large Number of Enterprise Stores.	CEC	2004	DBLP DOI BibTeX RDF
28	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
28	Nianjun Zhou, Da Peng An, Liang-Jie Zhang, Chih-Hong Wong	Leveraging Cloud Platform for Custom Application Development.	IEEE SCC	2011	DBLP DOI BibTeX RDF	custom application development, solution workbench, project assembly, cloud image, team collaboration, asset reuse, cloud computing, project management
28	Marcio Juliato, Catherine H. Gebotys	Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals.	ReConFig	2009	DBLP DOI BibTeX RDF	Processor Specialization, SHA-2, Cryptography, HMAC, HW/SW Partitioning, Co-Processor, Custom Instruction
28	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Rethinking custom ISE identification: a new processor-agnostic method.	CASES	2007	DBLP DOI BibTeX RDF	ISE identification, custom processors, maximal cluster
28	Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou	A custom FPGA for the simulation of gene regulatory networks.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	custom mixed signal FPGA, genetic pathways, gene regulatory networks
28	Pedro C. Diniz, Joonseok Park	Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures.	FCCM	2003	DBLP DOI BibTeX RDF	Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs)