Search results for "custom-instructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	Pan Yu, Tulika Mitra	Disjoint Pattern Enumeration for Custom Instructions Identification.	FPL	2007	DBLP DOI BibTeX RDF
65	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
64	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
61	Pan Yu, Tulika Mitra	Scalable custom instructions identification for instruction-set extensible processors.	CASES	2004	DBLP DOI BibTeX RDF	subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
60	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Custom-instruction synthesis for extensible-processor platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
54	Huynh Phung Huynh, Tulika Mitra	Runtime Adaptive Extensible Embedded Processors - A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
53	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
53	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
52	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.	VLSI Design	2008	DBLP DOI BibTeX RDF
52	Pan Yu, Tulika Mitra	Satisfying real-time constraints with custom instructions.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	real-time systems, execution time, instruction-set extensions, worst-case, customizable processors
49	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
47	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi	Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor.	DATE	2007	DBLP DOI BibTeX RDF
46	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue	An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
43	Najwa Aaraj, Anand Raghunathan, Niraj K. Jha	Analysis and design of a hardware/software trusted platform module for embedded systems.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded systems, multiprocessor systems, Custom instructions
42	Quang Dinh, Deming Chen, Martin D. F. Wong	Efficient ASIP design for configurable processors with fine-grained resource sharing.	FPGA	2008	DBLP DOI BibTeX RDF	multi-cycle IO, compilation, ASIP, resource sharing, configurable processor
42	Robert G. Dimond, Oskar Mencer, Wayne Luk	Automating processor customisation: optimised memory access and resource sharing.	DATE	2006	DBLP DOI BibTeX RDF
41	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
39	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Scalable Synthesis Methodology for Application-Specific Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
37	Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk	CHIPS: Custom Hardware Instruction Processor Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
37	Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan	Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors.	DELTA	2006	DBLP DOI BibTeX RDF
37	Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic	Hardware/software managed scratchpad memory for embedded system.	ICCAD	2004	DBLP DOI BibTeX RDF
36	Johann Großschädl, Erkay Savas	Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m).	CHES	2004	DBLP DOI BibTeX RDF
35	Xiaoyong Chen, Douglas L. Maskell, Yang Sun	Fast Identification of Custom Instructions for Extensible Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
33	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Application-specific heterogeneous multiprocessor synthesis using extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
33	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
32	Tao Li 0008, Zhigang Sun, Wu Jigang, Xicheng Lu	Fast enumeration of maximal valid subgraphs for custom-instruction identification.	CASES	2009	DBLP DOI BibTeX RDF	ISE identification, custom processors, maximal subgraph
32	Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour	An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
31	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
28	Xiaoyong Chen, Douglas L. Maskell	M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors.	ARCS	2006	DBLP DOI BibTeX RDF
27	Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra	Exploiting forwarding to improve data bandwidth of instruction-set extensions.	DAC	2006	DBLP DOI BibTeX RDF	instruction-set extensions, data forwarding
26	Stefan Tillich, Johann Großschädl	VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors.	WAIFI	2007	DBLP DOI BibTeX RDF
26	Johann Großschädl, Guy-Armand Kamendje	Optimized RISC Architecture for Multiple-Precision Modular Arithmetic.	SPC	2003	DBLP DOI BibTeX RDF	RSA Algorithm, Finely IntegratedOperand Scanning (FIOS), Multi-Application Smart Cards, Montgomery Multiplication
25	Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang 0001	RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
25	Shanshan Wang, Chenglong Xiao	Reinforcement Learning for Selecting Custom Instructions Under Area Constraint.	IEEE Trans. Artif. Intell.	2024	DBLP DOI BibTeX RDF
25	Eymen Ünay, Bora Inan, Emrecan Yigit	Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor.	CoRR	2023	DBLP DOI BibTeX RDF
25	Peiran Du, Zhaohui Cai	A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions.	ICA3PP (1)	2023	DBLP DOI BibTeX RDF
25	Tim Todman, Wayne Luk	Custom Instructions for Networked Processor Templates.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
25	Chao Wang 0003, Lei Gong, Fahui Jia, Xuehai Zhou	An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
25	Che-Chia Lin, Chao-Lin Lee, Jenq-Kuen Lee, Howard Wang, Ming-Yu Hung	Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions.	ICPP Workshops	2021	DBLP DOI BibTeX RDF
25	Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor	A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism.	ACM Trans. Embed. Comput. Syst.	2020	DBLP DOI BibTeX RDF
25	Shanshan Wang, Chenglong Xiao, Wanjun Liu	Parallel Enumeration of Custom Instructions Based on Multidepth Graph Partitioning.	IEEE Embed. Syst. Lett.	2019	DBLP DOI BibTeX RDF
25	Markku-Juhani O. Saarinen	SNEIK on Microcontrollers: AVR, ARMv7-M, and RISC-V with Custom Instructions.	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
25	Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna	CIDPro: Custom Instructions for Dynamic Program Diversification.	CoRR	2018	DBLP BibTeX RDF
25	Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna	CIDPro: Custom Instructions for Dynamic Program Diversification.	FPL	2018	DBLP DOI BibTeX RDF
25	Hu Chen, Shuming Chen	Fast automatic generation of efficient custom instructions for application-aware computing.	ICACI	2018	DBLP DOI BibTeX RDF
25	Ioannis Latifis	A MATLAB to C vectoring compiler exploiting custom instructions of targeted processors		2017	RDF
25	Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram	Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions.	ACM Trans. Design Autom. Electr. Syst.	2016	DBLP DOI BibTeX RDF
25	Hanno Scharwächter	Automatic identification and utilization of custom instructions for network processors.		2016	RDF
25	Bouthaina Dammak, Mouna Baklouti, Rachid Benmansour, Smaïl Niar, Mohamed Abid	Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner.	IEEE Embed. Syst. Lett.	2015	DBLP DOI BibTeX RDF
25	Emanuele Giaquinta, Anadi Mishra, Laura Pozzi	Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
25	Cecilia González-Alvarez	Automated design of domain-specific custom instructions = Geautomatiseerd ontwerp van domeinspecifieke gespecialiseerde instructies.		2015	RDF
25	Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan	Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.	ACM Trans. Reconfigurable Technol. Syst.	2014	DBLP DOI BibTeX RDF
25	Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram	Improving efficiency of extensible processors by using approximate custom instructions.	DATE	2014	DBLP DOI BibTeX RDF
25	Hui Huang, Taemin Kim, Yatin Hoskote	Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design.	ASP-DAC	2014	DBLP DOI BibTeX RDF
25	Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan	FPGA-aware techniques for rapid generation of profitable custom instructions.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
25	Junwhan Ahn, Kiyoung Choi	Isomorphism-Aware Identification of Custom Instructions With I/O Serialization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
25	Jason Cong, Karthik Gururaj	Architecture support for custom instructions with memory operations.	FPGA	2013	DBLP DOI BibTeX RDF
25	Ali Azarpeyvand, Mostafa E. Salehi, Sied Mehdi Fakhraie	Vulnerability Analysis for Custom Instructions.	DSD	2012	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke	Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration.	ReCoSoC	2012	DBLP DOI BibTeX RDF
25	Suvarna Mane, Mostafa M. I. Taha, Patrick Schaumont	Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA.	FPL	2012	DBLP DOI BibTeX RDF
25	Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan	Custom instructions with local memory elements without expensive DMA transfers.	FPL	2012	DBLP DOI BibTeX RDF
25	Antoine Trouvé, Kazuaki J. Murakami	Augmenting DR-ASIP flexibility through multi-mode custom instructions.	SIGARCH Comput. Archit. News	2011	DBLP DOI BibTeX RDF
25	Tao Li 0008, Jigang Wu, Yun Deng, Thambipillai Srikanthan, Xicheng Lu	Accelerating identification of custom instructions for extensible processors.	IET Circuits Devices Syst.	2011	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke	Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
25	Tao Li 0008, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu	Selecting profitable custom instructions for reconfigurable processors.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
25	Huynh Phung Huynh, Yun Liang 0001, Tulika Mitra	Efficient custom instructions generation for system-level design.	FPT	2010	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke	Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.	IEEE Trans. Ind. Electron.	2009	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang	Run-time management of custom instructions on a partially reconfigurable architecture.	Int. J. Inf. Commun. Technol.	2009	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan	Rapid design of area-efficient custom instructions for reconfigurable embedded processing.	J. Syst. Archit.	2009	DBLP DOI BibTeX RDF
25	Huynh Phung Huynh, Tulika Mitra	Runtime reconfiguration of custom instructions for real-time embedded systems.	DATE	2009	DBLP DOI BibTeX RDF
25	Marcio Juliato, Catherine H. Gebotys	Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals.	ReConFig	2009	DBLP DOI BibTeX RDF	Processor Specialization, SHA-2, Cryptography, HMAC, HW/SW Partitioning, Co-Processor, Custom Instruction
25	Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki J. Murakami	A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
25	Mark White, Tai-Chi Lee, Michael Gubody	Blowfish Encryption/Decryption Using FPGA and Custom Instructions.	PDPTA	2008	DBLP BibTeX RDF
25	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
25	Kang Zhao, Jinian Bian, Sheqin Dong	A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design.	CSCWD	2007	DBLP DOI BibTeX RDF
25	Paolo Bonzini, Laura Pozzi	A Retargetable Framework for Automated Discovery of Custom Instructions.	ASAP	2007	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan	Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors.	ASAP	2007	DBLP DOI BibTeX RDF
25	Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke	Rapid generation of custom instructions using predefined dataflow structures.	Microprocess. Microsystems	2006	DBLP DOI BibTeX RDF
25	Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara	Contribution of Custom Instructions on SoPC for iris recognition application.	ICECS	2006	DBLP DOI BibTeX RDF
25	Tai-Chi Lee, Richard Zeien, Adam Roach, Patrick Robinson	DES Decoding Using FPGA and Custom Instructions.	ITNG	2006	DBLP DOI BibTeX RDF	Security, Parallel Processing, Encryption, Encoder, Decoder, DES, Decryption
25	Siew Kei Lam, Bharathi N. Krishnan, Thambipillai Srikanthan	Efficient management of custom instructions for run-time reconfigurable instruction set processors.	FPT	2006	DBLP DOI BibTeX RDF
25	Haichen Ren, David Jeff Jackson	Morphological Image Processing Using Custom Instructions on Distributed Nios Processors.	CATA	2004	DBLP BibTeX RDF
22	Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani	An architecture framework for an adaptive extensible processor.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Reconfigurable functional unit, Profiling, Temporal partitioning, Custom instruction, Extensible processor, Similarity detection
22	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
22	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Energy Estimation for Extensible Processors.	DATE	2003	DBLP DOI BibTeX RDF
21	Abbas Bigdeli, Colin Sim, Morteza Biglari-Abhari, Brian C. Lovell	Face Detection on Embedded Systems.	ICESS	2007	DBLP DOI BibTeX RDF
21	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi	Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.	EUC	2006	DBLP DOI BibTeX RDF
21	Eugene Hyun, Mihai Sima, Michael McGuire	Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor.	CCECE	2006	DBLP DOI BibTeX RDF
21	Samik Das, P. P. Chakrabarti 0001, Pallab Dasgupta	Instruction-Set-Extension Exploration Using Decomposable Heuristic Search.	VLSI Design	2006	DBLP DOI BibTeX RDF
21	Stefan Tillich, Johann Großschädl	Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography.	ICCSA (2)	2005	DBLP DOI BibTeX RDF	32-bit implementation, software acceleration, Advanced Encryption Standard, Rijndael, instruction set extensions
21	Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner	An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors.	ISCA	2005	DBLP DOI BibTeX RDF
21	Raymond Hoare, Shen Chih Tung, Katrina Werger	An 88-Way Multiprocessor within an FPGA with Customizable Instructions.	IPDPS	2004	DBLP DOI BibTeX RDF	FPGA, Architecture, Parallelism, DSP, SIMD
20	Carlo Galuzzi	Introduction to Instruction-Set Customization.	SAMOS	2009	DBLP DOI BibTeX RDF
16	Hai Lin 0004, Yunsi Fei	A novel multi-objective instruction synthesis flow for application-specific instruction set processors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	instruction set synthesis, application-specific instruction set processor (ASIP)
16	Paolo Bonzini, Laura Pozzi	Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Marcio Juliato, Guido Araujo, Julio César López-Hernández, Ricardo Dahab	A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Gaussian normal bases, processor specialization, elliptic curve cryptography, finite field arithmetic
16	Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir	Supporting multithreading in configurable soft processor cores.	CASES	2007	DBLP DOI BibTeX RDF	soft processor cores, multithreading
16	Feng Xian, Witawas Srisa-an, Hong Jiang 0001	Evaluating Hardware Support for Reference Counting Using Software Configurable Processors.	ASAP	2006	DBLP DOI BibTeX RDF
15	Tobias Vejda, Dan Page, Johann Großschädl	Instruction Set Extensions for Pairing-Based Cryptography.	Pairing	2007	DBLP DOI BibTeX RDF