Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Pan Yu, Tulika Mitra |
Disjoint Pattern Enumeration for Custom Instructions Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 273-278, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
65 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 551-556, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
64 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11), pp. 2035-2045, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Pan Yu, Tulika Mitra |
Scalable custom instructions identification for instruction-set extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 69-78, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors |
60 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Custom-instruction synthesis for extensible-processor platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2), pp. 216-228, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Huynh Phung Huynh, Tulika Mitra |
Runtime Adaptive Extensible Embedded Processors - A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 215-225, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
53 | Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge |
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 92-, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions |
53 | Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski |
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 69-76, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 348-353, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Pan Yu, Tulika Mitra |
Satisfying real-time constraints with custom instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 166-171, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
real-time systems, execution time, instruction-set extensions, worst-case, customizable processors |
49 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 473-476, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Maziar Goudarzi |
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 325-330, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue |
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 219-230, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
Analysis and design of a hardware/software trusted platform module for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(1), pp. 8:1-8:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, multiprocessor systems, Custom instructions |
42 | Quang Dinh, Deming Chen, Martin D. F. Wong |
Efficient ASIP design for configurable processors with fine-grained resource sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 99-106, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-cycle IO, compilation, ASIP, resource sharing, configurable processor |
42 | Robert G. Dimond, Oskar Mencer, Wayne Luk |
Automating processor customisation: optimised memory access and resource sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 206-211, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi |
Compiling custom instructions onto expression-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 51-60, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures |
39 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
A Scalable Synthesis Methodology for Application-Specific Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(11), pp. 1175-1188, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk |
CHIPS: Custom Hardware Instruction Processor Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 528-541, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan |
Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 237-242, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
Hardware/software managed scratchpad memory for embedded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 370-377, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Johann Großschädl, Erkay Savas |
Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 133-147, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoyong Chen, Douglas L. Maskell, Yang Sun |
Fast Identification of Custom Instructions for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 359-368, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Application-specific heterogeneous multiprocessor synthesis using extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1589-1602, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
A Scalable Application-Specific Processor Synthesis Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 283-290, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Tao Li 0008, Zhigang Sun, Wu Jigang, Xicheng Lu |
Fast enumeration of maximal valid subgraphs for custom-instruction identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 29-36, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ISE identification, custom processors, maximal subgraph |
32 | Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour |
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 151-156, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 816-829, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Xiaoyong Chen, Douglas L. Maskell |
M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 191-201, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra |
Exploiting forwarding to improve data bandwidth of instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 43-48, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction-set extensions, data forwarding |
26 | Stefan Tillich, Johann Großschädl |
VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAIFI ![In: Arithmetic of Finite Fields, First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings, pp. 40-54, 2007, Springer, 978-3-540-73073-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Johann Großschädl, Guy-Armand Kamendje |
Optimized RISC Architecture for Multiple-Precision Modular Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPC ![In: Security in Pervasive Computing, First International Conference, Boppard, Germany, March 12-14, 2003, Revised Papers, pp. 253-270, 2003, Springer, 3-540-20887-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
RSA Algorithm, Finely IntegratedOperand Scanning (FIOS), Multi-Application Smart Cards, Montgomery Multiplication |
25 | Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang 0001 |
RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(2), pp. 523-535, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Shanshan Wang, Chenglong Xiao |
Reinforcement Learning for Selecting Custom Instructions Under Area Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Artif. Intell. ![In: IEEE Trans. Artif. Intell. 5(4), pp. 1882-1894, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Eymen Ünay, Bora Inan, Emrecan Yigit |
Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.18353, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Peiran Du, Zhaohui Cai |
A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (1) ![In: Algorithms and Architectures for Parallel Processing - 23rd International Conference, ICA3PP 2023, Tianjin, China, October 20-22, 2023, Proceedings, Part I, pp. 439-454, 2023, Springer, 978-981-97-0833-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Tim Todman, Wayne Luk |
Custom Instructions for Networked Processor Templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(7), pp. 3096-3100, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Chao Wang 0003, Lei Gong, Fahui Jia, Xuehai Zhou |
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 70(5), pp. 725-732, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Che-Chia Lin, Chao-Lin Lee, Jenq-Kuen Lee, Howard Wang, Ming-Yu Hung |
Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: ICPP Workshops 2021: 50th International Conference on Parallel Processing, Virtual Event / Lemont (near Chicago), IL, USA, August 9-12, 2021, pp. 15:1-15:8, 2021, ACM, 978-1-4503-8441-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor |
A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 19(6), pp. 50:1-50:27, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Shanshan Wang, Chenglong Xiao, Wanjun Liu |
Parallel Enumeration of Custom Instructions Based on Multidepth Graph Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 11(1), pp. 1-4, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Markku-Juhani O. Saarinen |
SNEIK on Microcontrollers: AVR, ARMv7-M, and RISC-V with Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2019, pp. 936, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
25 | Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna |
CIDPro: Custom Instructions for Dynamic Program Diversification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1809.01221, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
25 | Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna |
CIDPro: Custom Instructions for Dynamic Program Diversification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, August 27-31, 2018, pp. 224-229, 2018, IEEE Computer Society, 978-1-5386-8517-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Hu Chen, Shuming Chen |
Fast automatic generation of efficient custom instructions for application-aware computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACI ![In: Tenth International Conference on Advanced Computational Intelligence, ICACI 2018, Xiamen, China, March 29-31, 2018, pp. 283-288, 2018, IEEE, 978-1-5386-4362-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Ioannis Latifis |
A MATLAB to C vectoring compiler exploiting custom instructions of targeted processors ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2017 |
RDF |
|
25 | Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram |
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 21(2), pp. 28:1-28:25, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Hanno Scharwächter |
Automatic identification and utilization of custom instructions for network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2016 |
RDF |
|
25 | Bouthaina Dammak, Mouna Baklouti, Rachid Benmansour, Smaïl Niar, Mohamed Abid |
Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 7(4), pp. 105-108, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Emanuele Giaquinta, Anadi Mishra, Laura Pozzi |
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3), pp. 483-494, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Cecilia González-Alvarez |
Automated design of domain-specific custom instructions = Geautomatiseerd ontwerp van domeinspecifieke gespecialiseerde instructies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
25 | Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan |
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 7(3), pp. 26:1-26:15, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram |
Improving efficiency of extensible processors by using approximate custom instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-4, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Hui Huang, Taemin Kim, Yatin Hoskote |
Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014, pp. 219-224, 2014, IEEE, 978-1-4799-2816-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan |
FPGA-aware techniques for rapid generation of profitable custom instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(3), pp. 259-269, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Junwhan Ahn, Kiyoung Choi |
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1), pp. 34-46, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Jason Cong, Karthik Gururaj |
Architecture support for custom instructions with memory operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013, pp. 231-234, 2013, ACM, 978-1-4503-1887-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Ali Azarpeyvand, Mostafa E. Salehi, Sied Mehdi Fakhraie |
Vulnerability Analysis for Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012, pp. 144-147, 2012, IEEE Computer Society, 978-1-4673-2498-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke |
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012, pp. 1-8, 2012, IEEE, 978-1-4673-2570-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Suvarna Mane, Mostafa M. I. Taha, Patrick Schaumont |
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 20-25, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Alok Prakash, Christopher T. Clarke, Thambipillai Srikanthan |
Custom instructions with local memory elements without expensive DMA transfers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 647-650, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Antoine Trouvé, Kazuaki J. Murakami |
Augmenting DR-ASIP flexibility through multi-mode custom instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 39(4), pp. 90-93, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Tao Li 0008, Jigang Wu, Yun Deng, Thambipillai Srikanthan, Xicheng Lu |
Accelerating identification of custom instructions for extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 5(1), pp. 21-32, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke |
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(5), pp. 680-692, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Tao Li 0008, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu |
Selecting profitable custom instructions for reconfigurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 56(8), pp. 340-351, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Huynh Phung Huynh, Yun Liang 0001, Tulika Mitra |
Efficient custom instructions generation for system-level design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, pp. 445-448, 2010, IEEE, 978-1-4244-8981-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke |
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 56(10), pp. 3998-4005, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang |
Run-time management of custom instructions on a partially reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Commun. Technol. ![In: Int. J. Inf. Commun. Technol. 2(1/2), pp. 50-59, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan |
Rapid design of area-efficient custom instructions for reconfigurable embedded processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 55(1), pp. 1-14, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Huynh Phung Huynh, Tulika Mitra |
Runtime reconfiguration of custom instructions for real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, pp. 1536-1541, 2009, IEEE, 978-1-4244-3781-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Marcio Juliato, Catherine H. Gebotys |
Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 195-200, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Processor Specialization, SHA-2, Cryptography, HMAC, HW/SW Partitioning, Co-Processor, Custom Instruction |
25 | Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki J. Murakami |
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(4), pp. 497-508, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Mark White, Tai-Chi Lee, Michael Gubody |
Blowfish Encryption/Decryption Using FPGA and Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008, Las Vegas, Nevada, USA, July 14-17, 2008, 2 Volumes, pp. 164-169, 2008, CSREA Press, 1-60132-084-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
25 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 261-266, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Kang Zhao, Jinian Bian, Sheqin Dong |
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 121-126, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Paolo Bonzini, Laura Pozzi |
A Retargetable Framework for Automated Discovery of Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 334-341, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan |
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 89-94, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke |
Rapid generation of custom instructions using predefined dataflow structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 30(6), pp. 355-366, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Thomas Ea, Frédéric Amiel, Alicja Michalowska, Florence Rossant, Amara Amara |
Contribution of Custom Instructions on SoPC for iris recognition application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 455-458, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Tai-Chi Lee, Richard Zeien, Adam Roach, Patrick Robinson |
DES Decoding Using FPGA and Custom Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 575-577, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Security, Parallel Processing, Encryption, Encoder, Decoder, DES, Decryption |
25 | Siew Kei Lam, Bharathi N. Krishnan, Thambipillai Srikanthan |
Efficient management of custom instructions for run-time reconfigurable instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006, pp. 261-264, 2006, IEEE, 0-7803-9728-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Haichen Ren, David Jeff Jackson |
Morphological Image Processing Using Custom Instructions on Distributed Nios Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: 19th International Conference on Computers and Their Applications, CATA 2004, March 18-20, 2004, Red Lion Hotel on Fifth Avenue, Seattle, Washington, USA, pp. 25-28, 2004, ISCA, 1-880843-50-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
22 | Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani |
An architecture framework for an adaptive extensible processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 45(3), pp. 313-340, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Reconfigurable functional unit, Profiling, Temporal partitioning, Custom instruction, Extensible processor, Similarity detection |
22 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 62-67, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
22 | Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
A hybrid energy-estimation technique for extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 652-664, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
Energy Estimation for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10682-10687, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Abbas Bigdeli, Colin Sim, Morteza Biglari-Abhari, Brian C. Lovell |
Face Detection on Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 295-308, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi |
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 722-731, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Eugene Hyun, Mihai Sima, Michael McGuire |
Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1052-1055, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Samik Das, P. P. Chakrabarti 0001, Pallab Dasgupta |
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 293-298, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Stefan Tillich, Johann Großschädl |
Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2005, International Conference, Singapore, May 9-12, 2005, Proceedings, Part II, pp. 665-675, 2005, Springer, 3-540-25861-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
32-bit implementation, software acceleration, Advanced Encryption Standard, Rijndael, instruction set extensions |
21 | Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner |
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 272-283, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Raymond Hoare, Shen Chih Tung, Katrina Werger |
An 88-Way Multiprocessor within an FPGA with Customizable Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Architecture, Parallelism, DSP, SIMD |
20 | Carlo Galuzzi |
Introduction to Instruction-Set Customization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 193, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Hai Lin 0004, Yunsi Fei |
A novel multi-objective instruction synthesis flow for application-specific instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 409-412, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
instruction set synthesis, application-specific instruction set processor (ASIP) |
16 | Paolo Bonzini, Laura Pozzi |
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1259-1267, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Marcio Juliato, Guido Araujo, Julio César López-Hernández, Ricardo Dahab |
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F2163 using Gaussian Normal Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(1), pp. 59-76, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Gaussian normal bases, processor specialization, elliptic curve cryptography, finite field arithmetic |
16 | Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir |
Supporting multithreading in configurable soft processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 155-159, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
soft processor cores, multithreading |
16 | Feng Xian, Witawas Srisa-an, Hong Jiang 0001 |
Evaluating Hardware Support for Reference Counting Using Software Configurable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 297-302, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Tobias Vejda, Dan Page, Johann Großschädl |
Instruction Set Extensions for Pairing-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pairing ![In: Pairing-Based Cryptography - Pairing 2007, First International Conference, Tokyo, Japan, July 2-4, 2007, Proceedings, pp. 208-224, 2007, Springer, 978-3-540-73488-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|