Search results for "d3l"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
37	Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello	New performance/power/area efficient, reliable full adder design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	d3l, reliability, dynamic, full-adder, sub-threshold
34		D3L: Decomposition of 3D Rotation and Lift from 2D Joint to 3D for Human Mesh Recovery.	CoRR	2023	DBLP DOI BibTeX RDF
34	Xianghui Wang, Zhiyong Feng 0002, Keman Huang	D3L-Based Service Runtime Self-Adaptation Using Replanning.	IEEE Access	2018	DBLP DOI BibTeX RDF
34	Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry	A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
34	Xiaofei Zhao, Dongping Tian, Limin Chen, Zhongzhi Shi	Reasoning Theory for D3L with Compositional Bridge Rules.	Intelligent Information Processing	2012	DBLP DOI BibTeX RDF
34	Shirin Pourashraf, Sayed Masoud Sayedi	A low power D3L 16-bit radix- 4 pipelined SRT divider.	CCECE	2012	DBLP DOI BibTeX RDF
34	Fabio Frustaci, Marco Lanuzza	A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.	PATMOS	2009	DBLP DOI BibTeX RDF
34	Jia Di, Fengwei Yang	D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
34	Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith	Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
34	Ramin Rafati, Sied Mehdi Fakhraie, Kenneth C. Smith	Low-power data-driven dynamic logic (D3L) [CMOS devices].	ISCAS	2000	DBLP DOI BibTeX RDF
33	Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.	VLSI Design	2009	DBLP DOI BibTeX RDF

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