Search results for "dcvsl"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
161	Jae-Joon Kim, Kaushik Roy 0001	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
103	Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi	Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
34	Sepideh Valiollahi, Gholamreza Ardeshir	An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all-digital time-based quantization.	Int. J. Circuit Theory Appl.	2019	DBLP DOI BibTeX RDF
34	Weiwei Ge, Lijuan Han, Yuan Cao 0003, Enyi Yao, Xiaojin Zhao	A Novel Low Voltage DCVSL Circuit Design based on Wilson Current Mirror.	APCCAS	2018	DBLP DOI BibTeX RDF
34	Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda	On Improving the Performance of Dynamic DCVSL Circuits.	J. Electr. Comput. Eng.	2017	DBLP DOI BibTeX RDF
34	Hadar Dagan, Adam Teman, Evgeny Pikhay, Vladislav Dayan, Anatoli Mordakhay, Yakov Roizin, Alexander Fish	A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
34	Ho Joon Lee, Yong-Bin Kim	Low power Null Convention Logic circuit design based on DCVSL.	MWSCAS	2013	DBLP DOI BibTeX RDF
34	Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio	A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
34	José F. da Rocha, Marcelino Bicho Dos Santos, José M. Dores Costa, Floriberto A. Lima	Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter.	IEEE Trans. Ind. Electron.	2008	DBLP DOI BibTeX RDF
34	Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada	Pre-conditioning Free Footless DCVSL for High-performance Datapaths.	ICECS	2006	DBLP DOI BibTeX RDF
34	Xunwei Wu, Guoqiang Hang, Massoud Pedram	Low power DCVSL circuits employing AC power supply.	Sci. China Ser. F Inf. Sci.	2002	DBLP DOI BibTeX RDF
33	MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada	Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dcvsl, high speed digital, pipeline, error detect, soft error
33	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
23	Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda	Measurement of power supply noise tolerance of self-timed processor.	DDECS	2009	DBLP DOI BibTeX RDF
23	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	Design for Self-Checking and Self-Timed Datapath.	VTS	2003	DBLP DOI BibTeX RDF	asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits
23	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A Totally Self-Checking Dynamic Asynchronous Datapath.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider
23	Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.	PATMOS	2000	DBLP DOI BibTeX RDF
23	Madhuban Kishor, José Pineda de Gyvez	Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families.	DFT	2000	DBLP DOI BibTeX RDF
23	Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi	An Asynchronous Morphological Processor for Multi-Media Applications.	VLSI Design	1997	DBLP DOI BibTeX RDF
23	Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry	Differential BiCMOS logic circuits: fault characterization and design-for-testability.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF