|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 8 occurrences of 8 keywords
|
|
|
Results
Found 20 publication records. Showing 20 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
161 | Jae-Joon Kim, Kaushik Roy 0001 |
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 549-552, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
103 | Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi |
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 283-288, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Sepideh Valiollahi, Gholamreza Ardeshir |
An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all-digital time-based quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 47(9), pp. 1417-1434, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Weiwei Ge, Lijuan Han, Yuan Cao 0003, Enyi Yao, Xiaojin Zhao |
A Novel Low Voltage DCVSL Circuit Design based on Wilson Current Mirror. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018, pp. 295-298, 2018, IEEE, 978-1-5386-8240-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, Jeebananda Panda |
On Improving the Performance of Dynamic DCVSL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2017, pp. 8207104:1-8207104:11, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
34 | Hadar Dagan, Adam Teman, Evgeny Pikhay, Vladislav Dayan, Anatoli Mordakhay, Yakov Roizin, Alexander Fish |
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(6), pp. 1497-1510, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Ho Joon Lee, Yong-Bin Kim |
Low power Null Convention Logic circuit design based on DCVSL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 29-32, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
34 | Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio |
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6), pp. 1225-1238, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | José F. da Rocha, Marcelino Bicho Dos Santos, José M. Dores Costa, Floriberto A. Lima |
Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 55(9), pp. 3315-3323, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Makoto Ikeda, Kin Hooi Dia, Kunihiro Asada |
Pre-conditioning Free Footless DCVSL for High-performance Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1053-1056, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Xunwei Wu, Guoqiang Hang, Massoud Pedram |
Low power DCVSL circuits employing AC power supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 45(3), pp. 232-240, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 177-180, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dcvsl, high speed digital, pipeline, error detect, soft error |
33 | Parag K. Lala, Anup Singh, Alvernon Walker |
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 238-246, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing |
23 | Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda |
Measurement of power supply noise tolerance of self-timed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 128-131, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
Design for Self-Checking and Self-Timed Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 417-430, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits |
23 | Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun |
A Totally Self-Checking Dynamic Asynchronous Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 27-32, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Totally self-checking asynchronous datapath, differential cascade voltage switch logic, divider |
23 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 195-204, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Madhuban Kishor, José Pineda de Gyvez |
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 349-357, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi |
An Asynchronous Morphological Processor for Multi-Media Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 336-341, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry |
Differential BiCMOS logic circuits: fault characterization and design-for-testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 437-445, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #20 of 20 (100 per page; Change: )
|
|