Search results for "digit-serial"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
151	Arash Hariri, Arash Reyhani-Masoleh	Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields.	WAIFI	2008	DBLP DOI BibTeX RDF	Shifted polynomial basis, binary extension fields, digit-serial, multiplication
145	Mary Jane Irwin, Robert Michael Owens	A case for digit serial VLSI signal processors.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
137	Krister Landernäs, Johnny Holmberg, Mark Vesterbacka	A high-speed low-latency digit-serial hybrid adder.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
117	Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani	Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
113	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
109	Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, In-Gil Nam	A New Digit-Serial Systolic Mulitplier for High Performance GF(2m) Applications.	HPCC	2005	DBLP DOI BibTeX RDF	VLSI, Cryptography, Finite Field, Digit-Serial Multiplier
107	Nam-Yeun Kim, Kee-Young Yoo	Digit-Serial AB2 Systolic Array for Division in GF(2m).	ICCSA (4)	2004	DBLP DOI BibTeX RDF
107	Hanho Lee, Gerald E. Sobelman	Digit-Serial DSP Library for Optimized FPGA Configuration.	FCCM	1998	DBLP DOI BibTeX RDF
95	Zhiyuan Yan	Digit-Serial Systolic Architectures for Inversions over GF(2m).	SiPS	2006	DBLP DOI BibTeX RDF
81	Markus Hütter, Johann Großschädl, Guy-Armand Kamendje	A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m).	ITCC	2003	DBLP DOI BibTeX RDF	binary extension fields, digit-serial/parallel multiplier, Elliptic curve cryptography, critical path
80	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over binary extension fields.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	security, finite field, normal basis, Digit-serial multiplier
78	Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong, Hiecheol Kim	A New Systolic Array for Least Significant Digit First Multiplication in GF(2m).	ICCSA (3)	2004	DBLP DOI BibTeX RDF	Digit-Serial Architecture, VLSI, Cryptography, Systolic Array, Finite Field Multiplication
74	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
73	Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon	A digit-serial multiplier for finite field GF(2m).	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
63	Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo	Fast FPGA-based pipelined digit-serial/parallel multipliers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
59	Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong	A fast digit-serial systolic multiplier for finite field GF(2m).	ASP-DAC	2005	DBLP DOI BibTeX RDF
59	Won-Ho Lee, Keon-Jik Lee, Kee-Young Yoo	New Digit-Serial Systolic Arrays for Power-Sum and Division Operation in GF(2m).	ICCSA (3)	2004	DBLP DOI BibTeX RDF
59	Sungwook Kim, Gerald E. Sobelman	Efficient digit-serial FIR filters with skew-tolerant domino.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
59	Mohammad K. Ibrahim, Abulaziz Almulhem	Bit-level pipelined digit serial GF(2m) multiplier.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
57	Magnus Karlsson, Mark Vesterbacka	Digit-serial/parallel multipliers with improved throughput and latency.	ISCAS	2006	DBLP DOI BibTeX RDF
57	Pasin Israsena, S. Summerfield	Wave digital filters using digit serial 3-port adaptors.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
56	Keshab K. Parhi, Takao Nishitani	VLSI architectures for discrete wavelet transforms.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
54	Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor	FPGA-Based Structures for On-Line FFT and DCT.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic
53	Martin Novotný, Jan Schmidt	General Digit-Serial Normal Basis Multiplier with Distributed Overlap.	DSD	2007	DBLP DOI BibTeX RDF
53	Martin Novotný, Jan Schmidt	Two Architectures of a General Digit-Serial Normal Basis Multiplier.	DSD	2006	DBLP DOI BibTeX RDF
51	Lun Li, Mitchell A. Thornton, David W. Matula	A digit serial algorithm for the integer power operation.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power operation, standard cell implementation, exponential, discrete log
50	Steven D. Krueger, Peter-Michael Seidel	Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE rounding, Floating-point addition, on-line arithmetic
46	Leilei Song, Keshab K. Parhi	Efficient Finite Field Serial/Parallel Multiplication.	ASAP	1996	DBLP DOI BibTeX RDF	finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory
45	Junfeng Fan, Ingrid Verbauwhede	Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2m).	HOST	2008	DBLP DOI BibTeX RDF
45	Alex Fit-Florea, David W. Matula	A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.	ASAP	2004	DBLP DOI BibTeX RDF
44	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Digit pipelined arithmetic on fine-grain array processors.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
42	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
42	J. Living, Bashir M. Al-Hashimi	Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
42	M. C. Mekhallalati, Ahmed S. Ashur, M. K. Ibrahim	Novel Radix Finite Field Multiplier for GF(2m).	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
38	Sridhar Rajagopal, Joseph R. Cavallaro	Truncated Online Arithmetic with Applications to Communication Systems.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Dynamic truncation, finite precision, communication systems, online arithmetic
37	Monk-Ping Leong, Philip Heng Wai Leong	A variable-radix digit-serial design methodology and its application to the discrete cosine transform.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
37	Guido Bertoni, Jorge Guajardo, Gerardo Orlando	Systolic and Scalable Architectures for Digit-Serial Multiplication in Fields GF(pm).	INDOCRYPT	2003	DBLP DOI BibTeX RDF
37	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over GF(2m).	ISCAS (5)	2002	DBLP DOI BibTeX RDF
37	Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk	A Digit-Serial Structure for Reconfigurable Multipliers.	FPL	2001	DBLP DOI BibTeX RDF
37	Lori Lucke, Chaitali Chakrabarti	A digit-serial architecture for gray-scale morphological filtering.	IEEE Trans. Image Process.	1995	DBLP DOI BibTeX RDF
36	Jeng-Shyang Pan 0001, Chiou-Yng Lee, Pramod Kumar Meher	Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
34	Junfeng Fan, Lejla Batina, Ingrid Verbauwhede	Light-weight implementation options for curve-based cryptography: HECC is also ready for RFID.	ICITST	2009	DBLP DOI BibTeX RDF
34	G. K. Grigoriadis, Basil G. Mertzios	Implementation of the velocities of the end-effector with the distributed arithmetic architecture.	J. Intell. Robotic Syst.	1996	DBLP DOI BibTeX RDF	linear velocity, positional and orientational Jacobian matrices, distributed arithmetic and end-effector, pipelining, robot kinematics, fast implementation, angular velocity
34	Essam Elsayed, Hatem M. El-Boghdadi	Area-Efficient Digit Serial-Serial Two's Complement Multiplier.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
34	Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos	Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
34	Keon-Jik Lee, Kee-Won Kim, Kee-Young Yoo	Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm.	Inf. Process. Lett.	2002	DBLP DOI BibTeX RDF
34	Keon-Jik Lee, Kee-Won Kim, Kee-Young Yoo	Digit Serial-In-Serial-Out Systolic Multiplier for Montogomery's Algorithm.	PDCS	2001	DBLP BibTeX RDF
28	Peter Kornerup	A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
28	Milos D. Ercegovac, Tomás Lang	On-the-Fly Rounding.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	digit rounding, digit-serial form, most significant digit, least significant, redundant addition, result-digit, signed-digit set, computing arithmetic, digital arithmetic, number theory, digit-recurrence algorithms, online arithmetic
28	Milos D. Ercegovac, Tomás Lang	Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	online CORDIC, redundant CORDIC, matrix triangularization, angles, digit-serial addition, online multiplication, Givens' rotations, singular value decomposition, SVD, digital arithmetic, rotations, division, square root, scaling factors, floating-point representations
28	Franco P. Preparata, Jean Vuillemin	Practical Cellular Dividers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	parallel division algorithms, nonrestoring online division methods, divider/multiplier, RSA cryptography, greatest common divisor computations, parallel algorithms, signal processing, digital arithmetic, modular arithmetic, redundant representations, floating-point units, dividing circuits, signed, systolic, digit-serial multiplier
28	Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor	A FPGA-based Library for On-Line Signal Processing.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FFT, DSP, DCT, configurable computing, on-line arithmetic
26	Adnan Abdul-Aziz Gutub, Mohammad K. Ibrahim	Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	crypto-systems power-time tradeoff, projective coordinate arithmetic, parallel architecture, elliptic curve cryptography
26	Oscar Gustafsson, Lars Wanhammar	Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space representation.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
23	Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar, Jeong-A Lee	DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator.	CoRR	2023	DBLP DOI BibTeX RDF
23	Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar, Jeong-A Lee	DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator.	DSD	2023	DBLP DOI BibTeX RDF
23	Xinyu Wang, Ning Wu, Fang Zhou 0001, Fen Ge	Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m).	ICCT	2022	DBLP DOI BibTeX RDF
23	Shen-Fu Hsiao, Hung-Ching Li, Yu-Che Yen, Po-Chang Li	Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination.	ISCAS	2022	DBLP DOI BibTeX RDF
23	Hayssam El-Razouk, Kirthi Kotha, Mahidhar Puligunta	Novel $GF\left(2^{m}\right)$GF2m Digit-Serial PISO Multipliers for the Self-Dual Gaussian Normal Bases.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
23	Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu	Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation.	ISCAS	2021	DBLP DOI BibTeX RDF
23	Atef Ibrahim	Unified and Scalable Digit-Serial Systolic Array for Multiplication and Division Over GF (2m).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Jiafeng Xie	Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation.	ASP-DAC	2020	DBLP DOI BibTeX RDF
23	Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao	Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
23	Ned Bingham, Rajit Manohar	Self-Timed Adaptive Digit-Serial Addition.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
23	Sahar Fatemi, Maryam Zare, Amir Farzad Khavari, Mohammad Maymandi-Nejad	Efficient implementation of digit-serial Montgomery modular multiplier architecture.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
23	Atef Ibrahim	Scalable digit-serial processor array architecture for finite field division.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Jiafeng Xie	Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
23	Siva Ramakrishna Pillutla, Lakshmi Boppana	A high-throughput fully digit-serial polynomial basis finite field GF(2m) multiplier for IoT applications.	TENCON	2019	DBLP DOI BibTeX RDF
23	Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee	Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials.	IEEE Trans. Multi Scale Comput. Syst.	2018	DBLP DOI BibTeX RDF
23	Jeng-Shyang Pan 0001, Pengfei Song, Chun-Sheng Yang	Efficient digit-serial modular multiplication algorithm on FPGA.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
23	Zhenji Hu, Jiafeng Xie	Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m).	Symmetry	2018	DBLP DOI BibTeX RDF
23	Warren E. Ferguson, Jesse Bingham, Levent Erkök, John R. Harrison, Joe Leslie-Hurd	Digit Serial Methods with Applications to Division and Square Root.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
23	Jeng-Shyang Pan 0001, Shu-Xia Dong, Chun-Sheng Yang	Low-Space Complexity Digit-Serial Multiplier Based on Modified Polynomial Basis Over GF(2m).	J. Inf. Hiding Multim. Signal Process.	2017	DBLP BibTeX RDF
23	Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh, Jeng-Shyang Pan 0001	Low-latency digit-serial dual basis multiplier for lightweight cryptosystems.	IET Inf. Secur.	2017	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher, Chia-Chen Fan, Shyan-Ming Yuan	Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
23	Serdar Süer Erdem, Tugrul Yanik, Anil Çelebi	A General Digit-Serial Architecture for Montgomery Modular Multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
23	Shoaleh Hashemi Namin, Huapeng Wu, Majid Ahmadi	Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
23	Warren E. Ferguson, Jesse Bingham, Levent Erkök, John R. Harrison, Joe Leslie-Hurd	Digit Serial Methods with Applications to Division and Square Root (with mechanically checked correctness proofs).	CoRR	2017	DBLP BibTeX RDF
23	Atef Ibrahim, Fayez Gebali	Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ ).	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
23	Apostolos P. Fournaris, Charalambos Dimopoulos, Odysseas G. Koufopavlou	A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures.	DSD	2017	DBLP DOI BibTeX RDF
23	Atef Ibrahim, Turki F. Al-Somani, Fayez Gebali	Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices.	IEEE Access	2016	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu	Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
23	Abdalhossein Rezai, Parviz Keshavarzi	High-performance scalable architecture for modular multiplication using a new digit-serial computation.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
23	Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi	High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m).	IACR Cryptol. ePrint Arch.	2016	DBLP BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher	Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm".	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
23	Arash Reyhani-Masoleh	Comments on "Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2m) Using Subquadratic Toeplitz Matrix-Vector Product Approach".	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
23	Bilal Uslu, Serdar Süer Erdem	Versatile digit serial multipliers for binary extension fields.	Comput. Electr. Eng.	2015	DBLP DOI BibTeX RDF
23	Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher	Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher	Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher	Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
23	Shyan-Ming Yuan, Chiou-Yng Lee, Chia-Chen Fan	Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm.	ICGEC (2)	2015	DBLP DOI BibTeX RDF
23	Jeng-Shyang Pan 0001, Reza Azarderakhsh, Mehran Mozaffari Kermani, Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jim-Min Lin	Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan 0001	Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
23	Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee	Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm.	ISIC	2014	DBLP DOI BibTeX RDF
23	Wangchen Dai, Huapeng Wu, Ray C. C. Cheung	Time-efficient computation of digit serial Montgomery multiplication.	ISIC	2014	DBLP DOI BibTeX RDF
23	Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña	Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations.	IEEE Trans. Ind. Electron.	2013	DBLP DOI BibTeX RDF
23	Ying Yan Hua, Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Yong Huan Liu	Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2m) using Hankel matrix and Karatsuba algorithm.	IET Inf. Secur.	2013	DBLP DOI BibTeX RDF
23	Levent Aksoy, Cristiano Lazzari, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001	Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
23	Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos, René Cumplido	Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR.	Comput. Electr. Eng.	2013	DBLP DOI BibTeX RDF
23	Chun-Sheng Yang, Jeng-Shyang Pan 0001, Chiou-Yng Lee	Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m).	RVSP	2013	DBLP DOI BibTeX RDF