Search results for "eFPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
153	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP
117	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Design flow for embedded FPGAs based on a flexible architecture template.	DATE	2008	DBLP DOI BibTeX RDF
104	Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll	ASIP-eFPGA Architecture for Multioperable GNSS Receivers.	SAMOS	2008	DBLP DOI BibTeX RDF	arithmetic oriented eFPGA, multioperable GNSS, ASIP
70	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.	FPL	2007	DBLP DOI BibTeX RDF
70	Thorsten von Sydow, Bernd Neumann, Holger Blume, Tobias G. Noll	Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic.	ASAP	2006	DBLP DOI BibTeX RDF
70	Francesco Lertora, Michele Borgatti	Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip.	FCCM	2005	DBLP DOI BibTeX RDF
51	Victor O. Aken'Ova, Resve A. Saleh	A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm.	ISVLSI	2006	DBLP DOI BibTeX RDF
47	Götz Kappen, Tobias G. Noll	Application specific instruction processor based implementation of a GNSS receiver on an FPGA.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
29	Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres	Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	embedded FPGA, eFPGA accelerator, Reconfigurable computing, Power Consumption, MIPS
28	Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon	Secure eFPGA Configuration: A System-Level Approach.	ARC	2024	DBLP DOI BibTeX RDF
28	Praveen Karmakar, Marpina Bharani, Chandan Karfa	Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction.	VLSID	2024	DBLP DOI BibTeX RDF
28	Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri	Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
28	Morihiro Kuga, Qian Zhao 0001, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida	An eFPGA Generation Suite with Customizable Architecture and IDE.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2023	DBLP DOI BibTeX RDF
28	Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran	FuncTeller: How Well Does eFPGA Hide Functionality?	CoRR	2023	DBLP DOI BibTeX RDF
28	Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor	SheLL: Shrinking eFPGA Fabrics for Logic Locking.	DATE	2023	DBLP DOI BibTeX RDF
28	Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran	FuncTeller: How Well Does eFPGA Hide Functionality?	USENIX Security Symposium	2023	DBLP BibTeX RDF
28	Yunus Emre Eryilmaz, Hasan Erdem Yantir, Müstak E. Yalçin	An Open-Source eFPGA-based SoC Design for Computation Acceleration.	ICECS	2023	DBLP DOI BibTeX RDF
28	Fei Gao 0016, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu 0001, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff	DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.	CICC	2023	DBLP DOI BibTeX RDF
28	Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi	EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators.	DFT	2023	DBLP DOI BibTeX RDF
28	Sae Kyu Lee, Paul N. Whatmough, Marco Donato, Glenn G. Ko, David Brooks 0001, Gu-Yeon Wei	SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
28	Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato	ALICE: An Automatic Design Flow for eFPGA Redaction.	CoRR	2022	DBLP DOI BibTeX RDF
28	Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001, Imen Baili	Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA.	ISVLSI	2022	DBLP DOI BibTeX RDF
28	Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001, Juan Miguel De Haro Ruiz, Daniel Jiménez-González, Miquel Moretó, Carlos Álvarez 0001, Jesús Labarta, Imen Baili	Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.	DATE	2022	DBLP DOI BibTeX RDF
28	Amin Rezaei 0001, Raheel Afsharmazayejani, Jordan Maynard	Evaluating the Security of eFPGA-Based Redaction Algorithms.	ICCAD	2022	DBLP DOI BibTeX RDF
28	Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato	ALICE: an automatic design flow for eFPGA redaction.	DAC	2022	DBLP DOI BibTeX RDF
28	Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini	Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
28	Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri	Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction.	CoRR	2021	DBLP BibTeX RDF
28	Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri	Exploring eFPGA-based Redaction for IP Protection.	CoRR	2021	DBLP BibTeX RDF
28	Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai	Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion.	DATE	2021	DBLP DOI BibTeX RDF
28	Jing Yu 0014, Andrew Attwood, Nguyen Dao, Dirk Koch	The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams.	FPL	2021	DBLP DOI BibTeX RDF
28	Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri	Exploring eFPGA-based Redaction for IP Protection.	ICCAD	2021	DBLP DOI BibTeX RDF
28	Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini	Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes.	CoRR	2020	DBLP BibTeX RDF
28	Francesco Renzini, Claudio Mucci, Davide Rossi, Eleonora Franchi Scarselli, Roberto Canegallo	A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
28	Hajer Saidi, Mariem Turki, Zied Marrakchi, Abdulfattah Obeid, Mohamed Abid	Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes.	AICCSA	2020	DBLP DOI BibTeX RDF
28	Paul N. Whatmough, Sae Kyu Lee, Marco Donato, Hsea-Ching Hsueh, Sam Likun Xi, Udit Gupta, Lillian Pentecost, Glenn G. Ko, David M. Brooks, Gu-Yeon Wei	A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
28	Francesco Renzini, Davide Rossi, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo	A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications.	ICECS	2018	DBLP DOI BibTeX RDF
28	Matteo Cuppini, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo	Soft-core eFPGA for Smart Power applications.	ISSoC	2014	DBLP DOI BibTeX RDF
28	Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres	Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.	DATE	2009	DBLP DOI BibTeX RDF
28	Xinyu Li, Omar Hammami	Linear programming based design of reconfigurable network on chip on eFPGA.	ICECS	2008	DBLP DOI BibTeX RDF
28	Thorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume, Tobias G. Noll	Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros.	ReConFig	2006	DBLP DOI BibTeX RDF
28	Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh	An improved "soft" eFPGA design and implementation strategy.	CICC	2005	DBLP DOI BibTeX RDF