Search results for "flipflops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
61	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
53	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
41	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Partial Scan.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	deterministic scan-based BIST, partial scan
41	Hyoung B. Min, William A. Rogers	A test methodology for finite state machines using partial scan design.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	loop-free circuits, test generation, ATPG, fault, partial scan
41	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
33	Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula	A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
33	Parth Parekh, Fei Yuan 0005, Yushi Zhou	Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
33	Parth Parekh, Fei Yuan 0005, Yushi Zhou	Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability.	MWSCAS	2020	DBLP DOI BibTeX RDF
33	Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula	Fast and robust differential flipflops and their extension to multi-input threshold gates.	ISCAS	2015	DBLP DOI BibTeX RDF
33	Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
33	Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator.	NEWCAS	2012	DBLP DOI BibTeX RDF
33	Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops.	VLSIC	2012	DBLP DOI BibTeX RDF
33	Ning Chen 0006, Bing Li 0005, Ulf Schlichtmann	Timing Modeling of Flipflops Considering Aging Effects.	PATMOS	2011	DBLP DOI BibTeX RDF
33	Hiroki Sunagawa, Hidetoshi Onodera	Variation-tolerant design of D-flipflops.	SoCC	2010	DBLP DOI BibTeX RDF
33	Jiren Yuan, Christer Svensson	New single-clock CMOS latches and flipflops with improved speed and power savings.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
33	Klaus Lagemann	Ein Vorschlag zur Darstellung asynchron betriebener JK-Flipflops.	Elektron. Rechenanlagen	1968	DBLP DOI BibTeX RDF
33	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
20	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
20	Sanjay Burman, Debdeep Mukhopadhyay, Kamakoti Veezhinathan	LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.	INDOCRYPT	2007	DBLP DOI BibTeX RDF	Linear Feed Back Shift Registers, Dynamic Power Dissipation, Side Channel Attacks, Power Analysis, Hamming Distance
20	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
20	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
20	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Soft error reduction in combinational logic using gate resizing and flipflop selection.	ICCAD	2006	DBLP DOI BibTeX RDF
20	Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Logic SER Reduction through Flipflop Redesign.	ISQED	2006	DBLP DOI BibTeX RDF
20	Hans-Dieter Wohlmuth, Daniel Kehrer	A 24 GHz dual-modulus prescaler in 90nm CMOS.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
20	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
20	Sybille Hellebrand, Hans-Joachim Wunderlich	An efficient procedure for the synthesis of fast self-testable controller structures.	ICCAD	1994	DBLP DOI BibTeX RDF
20	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	The optimistic update theorem for path delay testing in sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	test generation, Fault simulation, timing analysis, path delay faults
20	Winfried Hahn, Kristian Fischer 0002	MuSiC: an event-flow computer for fast simulation of digital systems.	DAC	1985	DBLP DOI BibTeX RDF