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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 22 occurrences of 20 keywords
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Results
Found 62 publication records. Showing 62 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Gopalakrishnan Vijayan, Ren-Song Tsay |
A new method for floor planning using topological constraint reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12), pp. 1494-1501, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
62 | Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen |
Floor-Planning via Orderly Spanning Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 9th International Symposium, GD 2001 Vienna, Austria, September 23-26, 2001, Revised Papers, pp. 367-377, 2001, Springer, 3-540-43309-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
51 | Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim |
Profile-guided microarchitectural floor planning for deep submicron processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), pp. 1289-1300, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Grazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione |
ACCORDO: second generation floor planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 266-270, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
29 | Yi-Hui Cheng, Yao-Wen Chang |
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 624-627, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers |
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 250-256, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
28 | B. Lokanathan, Edwin Kinnen |
Performance optimized floor planning by graph planarization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 116-121, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin |
Automatic bus macro placement for partially reconfigurable FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 269-272, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning |
26 | Husain Parvez, Zied Marrakchi, Habib Mehrez |
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 121-126, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Coarse-grained FPGA, Exploration environment, Floor-planning |
26 | Jayaram Bhasker, Sartaj Sahni |
A linear algorithm to find a rectangular dual of a planar triangulated graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 108-114, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
planar triagulated graph, rectangular dual, algorithm, complexity, floor planning |
22 | Alexandra Melike Brintrup, Hideyuki Takagi, Jeremy J. Ramsden |
Evaluation of Sequential, Multi-objective, and Parallel Interactive Genetic Algorithms for Multi-objective Floor Plan Optimisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings, pp. 586-598, 2006, Springer, 3-540-33237-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Amit K. Gupta II, Appa Iyer Sivakumar, Sumit Sarawgi |
Scheduling & control: shop floor scheduling with simulation based proactive decision support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 34th Winter Simulation Conference: Exploring New Frontiers, San Diego, California, USA, December 8-11, 2002, pp. 1897-1902, 2002, WSC, 0-7803-7615-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Venkateswari Pichaimani, Manjula Ramakrishama Kalava |
Linear feature projective geometric damped convolutional deep belief network for indoor floor planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Fuzzy Syst. ![In: J. Intell. Fuzzy Syst. 44(4), pp. 6375-6386, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
17 | R. Karthick, A. Senthilselvi, P. Meenalochini |
An Optimal Partitioning and Floor Planning for VLSI Circuit Design Based on a Hybrid Bio-Inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(8), pp. 2350273:1-2350273:33, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Pushpalatha Pondreti, Babulu Kaparapu |
Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Swarm Intell. Res. ![In: Int. J. Swarm Intell. Res. 14(1), pp. 1-26, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
17 | S. B. Vinay Kumar, P. V. Rao, Manoj Kumar Singh |
Optimal floor planning in VLSI using improved adaptive particle swarm optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evol. Intell. ![In: Evol. Intell. 15(2), pp. 925-938, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | |
Positioning of WiFi devices for indoor floor planning using principal featured Kohonen deep structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 12(6), pp. 6841-6851, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Sivakumar Pothiraj, Jeya Prakash Kadambarajan, Pandiaraj Kadarkarai |
Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 118(4), pp. 3007-3023, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Jonathan Klawitter, Felix Klesen, Alexander Wolff 0001 |
Algorithms for Floor Planning with Proximity Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.05036, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
17 | Jonathan Klawitter, Felix Klesen, Alexander Wolff 0001 |
Algorithms for Floor Planning with Proximity Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAAD Futures ![In: Computer-Aided Architectural Design. Design Imperatives: The Future is Now - 19th International Conference, CAAD Futures 2021, Los Angeles, CA, USA, July 16-18, 2021, Selected Papers, pp. 151-171, 2021, Springer, 978-981-19-1279-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Hamide Ozlem Dalgic, Erkan Bostanci, Mehmet Serdar Güzel |
Genetic Algorithm Based Floor Planning System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1704.06016, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
17 | Makoto Inoue, Muneyuki Unehara, Koichi Yamada, Megumu Hiramoto, Hideyuki Takagi |
Evaluation of hybrid optimization with EMO and IEC for architectural floor planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCIS&ISIS ![In: 2014 Joint 7th International Conference on Soft Computing and Intelligent Systems (SCIS) and 15th International Symposium on Advanced Intelligent Systems (ISIS), Kita-Kyushu, Japan, December 3-6, 2014, pp. 54-61, 2014, IEEE, 978-1-4799-5955-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
17 | Paul Horn, Gabor Lippner |
Two Layer 3D Floor Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. J. Comb. ![In: Electron. J. Comb. 20(4), pp. 16, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
17 | Paul Horn, Gabor Lippner |
Two Layer 3D Floor Planning ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1210.4595, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
17 | Jaren Lamprecht, Brad L. Hutchings |
Profiling FPGA floor-planning effects on timing closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 151-156, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Huaming Zhang, Sadish Sadasivam |
Improved floor-planning of graphs via adjacency-preserving transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 22(4), pp. 726-746, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Makoto Inoue, Hideyuki Takagi |
EMO-based Architectural Room Floor Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, San Antonio, TX, USA, 11-14 October 2009, pp. 518-523, 2009, IEEE, 978-1-4244-2794-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna |
Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2008 East-West Design & Test Symposium, EWDTS 2008, Lviv, Ukraine, October 9-12, 2008, pp. 379-382, 2008, IEEE Computer Society, 978-1-4244-3402-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Maciej Kurowski |
Simple and efficient floor-planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 86(3), pp. 113-119, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen |
Compact floor-planning via orderly spanning trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Algorithms ![In: J. Algorithms 48(2), pp. 441-451, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Samir Roy, Sanghamitra Bandyopadhyay, Ujjwal Maulik |
Evolutionary Approach to Solve the Complex-Triangle Elimination (CTE) Problem of VLSI Floor-planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IICAI ![In: Proceedings of the 1st Indian International Conference on Artificial Intelligence, IICAI 2003, Hyderabad, India, December 18-20, 2003, pp. 646-655, 2003, IICAI, 0-9727412-0-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
17 | Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen |
Compact Floor-Planning via Orderly Spanning Trees ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR cs.DS/0210016, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
17 | Kok-Hoo Yeap, Majid Sarrafzadeh |
Floor-Planning by Graph Dualization: 2-Concave Rectilinear Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Comput. ![In: SIAM J. Comput. 22(3), pp. 500-526, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Christian Masson, Remy Escassut, Denis Barbier, Daniel Winer, Gregory Chevallier |
Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 259-264, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
LISP |
17 | Wing K. Luk, Alvar A. Dean, John W. Mathews |
Partitioning and floor-planning for data-path chip (microprocessor) layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 10(1), pp. 89-108, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Marwan A. Jabri, David J. Skellern |
PIAF: efficient IC floor planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Expert ![In: IEEE Expert 4(2), pp. 33-45, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Wing K. Luk, Alvar A. Dean, John W. Mathews |
Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers, pp. 492-495, 1989, IEEE Computer Society, 0-8186-1986-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Michael C. McFarland |
A fast floor planning algorithm for architectural evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 96-99, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Wayne Wei-Ming Dai, Ernest S. Kuh |
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5), pp. 828-837, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
17 | Yu-Chin Hsu |
Floor Planning and Global Routing in an Automated Chip Design System ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1987 |
RDF |
|
17 | Howard S. Rifkin, William R. Heller, Steve Law, Misha Burich, Alberto L. Sangiovanni-Vincentelli |
Floor planning systems (panel session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 630, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
14 | Victor O. Aken'Ova, Resve A. Saleh |
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 103-108, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Brett Feero, Partha Pratim Pande |
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(1), pp. 32-45, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Shashank Prasad, Anuj Kumar |
Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 399-403, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Yu Cheng 0001, Tao Zhang 0006, Song Chen |
VisionSynaptics: a system convert hand-writing and image symbol into computer symbol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIS ![In: Proceedings of the 2nd International Conference on Interaction Sciences: Information Technology, Culture and Human (ICIS 2009), Seoul, Korea, 24-26 November 2009, pp. 82-85, 2009, ACM, 978-1-60558-710-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
graphics segmenting, human-computer interaction, intelligent system, symbol recognition |
11 | Akshaya Kumar Mishra, Justin A. Eichel, Paul W. Fieguth, David A. Clausi |
VizDraw: A Platform to Convert Online Hand-Drawn Graphics into Computer Graphics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAR ![In: Image Analysis and Recognition, 6th International Conference, ICIAR 2009, Halifax, Canada, July 6-8, 2009. Proceedings, pp. 377-386, 2009, Springer, 978-3-642-02610-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Online hand-drawn diagram recognition, hypothesis generation and evaluation, stroke-based recognition |
11 | Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger |
An 8x8 run-time reconfigurable FPGA embedded in a SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 120-125, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, RTR |
11 | Lijun Gao, Keshab K. Parhi |
Models for Architectural Power and Power Grid Noise Analysis on Data Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(1-2), pp. 25-46, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
augmented DBT model, SCTA model, STCTA model, power consumption, switching activity, power spectrum, transition probability, power grid noise, transition activity |
11 | Rajarshi Mukhopadhyay, S. W. Yoon, Y. Park, Chang-Ho Lee, S. Nuttinck, Joy Laskar |
Investigation of inductors for digital Si-CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Alexandra Melike Brintrup, Jeremy J. Ramsden, Ashutosh Tiwari |
Integrated qualitativeness in design by multi-objective optimization and interactive evolutionary computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2005, 2-4 September 2005, Edinburgh, UK, pp. 2154-2160, 2005, IEEE, 0-7803-9363-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz |
The ISPD2005 placement contest and benchmark suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 216-220, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI placement, benchmarks, physical design |
11 | Chi-Sheng Shih 0001, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen |
Reconfigurable Platform for Content Science Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 481-486, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Liang Wu, Chi-Kong Chan |
On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAGA ![In: Stochastic Algorithms: Foundations and Applications, Third International Symposium, SAGA 2005, Moscow, Russia, October 20-22, 2005, Proceedings, pp. 70-81, 2005, Springer, 3-540-29498-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov |
Unification of partitioning, placement and floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 550-557, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Erik Larsson |
Integrating Core Selection in the SOC Test Solution Design-Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1349-1358, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri |
Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 193-197, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Erik Larsson, Hideo Fujiwara |
Test Resource Partitioning and Optimization for SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 319-324, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang |
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 69-75, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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11 | Michael Affenzeller, Franz Pichler, Rudolf Mittelmann |
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2001, Las Palmas de Gran Canaria, Spain, February 19-23, 2001, Revised Papers, pp. 36-44, 2001, Springer, 3-540-42959-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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11 | Kyumyung Choi, Steven P. Levitan |
A flexible datapath allocation method for architectural synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 4(4), pp. 376-404, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
allocation and binding, high-level synthesis |
11 | Christos A. Papachristou, Yusuf Alzazeri |
A Method of Distributed Controller Design for RTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 774-775, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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11 | Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky |
On wirelength estimations for row-based placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998, pp. 4-11, 1998, ACM, 1-58113-021-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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