Search results for "foundries"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
52	Matt Nowak, Riko Radojcic	Are there economic benefits in DFM?	DAC	2005	DBLP DOI BibTeX RDF	fabless, foundries, DFM, design for manufacturability
49	Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore	Analog intellectual property: now? Or never?	DAC	2002	DBLP DOI BibTeX RDF
46	Shang-yi Chiang	Foundries and the Dawn of an Open IP Era.	Computer	2001	DBLP DOI BibTeX RDF
33	Patrik Thollander	Barriers to and driving forces for the implementation of manufacturing simulation in the Swedish foundry industry.	WSC	2006	DBLP DOI BibTeX RDF
33	Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy	Differentiate and deliver: leveraging your partners.	DAC	2005	DBLP DOI BibTeX RDF	EDS, semiconductor fabrication, supplier-customer relationships, intellectual property, processors
33	Jacob K. White 0001, Gary K. Fedder, Tamal Mukherjee	Path toward future CAD environments for MEMS (tutorial abstract).	ICCAD	1999	DBLP DOI BibTeX RDF
29	Rahul Vishwakarma, Ravi Monani, Ava Hedayatipour, Amin Rezaei 0001	Reliable and secure memristor-based chaotic communication against eavesdroppers and untrusted foundries.	Discov. Internet Things	2023	DBLP DOI BibTeX RDF
29	Amin Rezaei 0001, Jie Gu 0001, Hai Zhou 0001	Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries.	IACR Cryptol. ePrint Arch.	2021	DBLP BibTeX RDF
29	Maria Gabriela S. Furtado, Victor Claudio Bento de Camargo, Franklina Maria Bragion Toledo	The production planning problem of orders in small foundries.	RAIRO Oper. Res.	2019	DBLP DOI BibTeX RDF
29	Timothy Trippel, Kang G. Shin, Kevin B. Bush, Matthew Hicks	An Extensible Framework for Quantifying the Coverage of Defenses Against Untrusted Foundries.	CoRR	2019	DBLP BibTeX RDF
29	Timothy Trippel, Kang G. Shin, Kevin B. Bush, Matthew Hicks	Defensive Routing: a Preventive Layout-Level Defense Against Untrusted Foundries.	CoRR	2019	DBLP BibTeX RDF
29	Amin Rezaei 0001, Jie Gu 0001, Hi Zhou	Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries.	ISVLSI	2019	DBLP DOI BibTeX RDF
29	Robert B. Allen, Yoonhwan Kim	Semantic Modeling with Foundries.	CoRR	2018	DBLP BibTeX RDF
29	Andy R. K. Chang, Yu-Ling Chen, Po-Yu Chou, Yen-Zhou Huang, Hung-Chang Hsiao, Tsung-Ting Hsieh, Michael Hsu, Chia-Chee Lee, Hsin-Yin Lee, Yun-Chi Shih, Wei-An Shih, Chien-Hsiang Tang, Chia-Ping Tsai, Kuan-Po Tseng	The Case of Big Data Platform Services for Semiconductor Wafer Fabrication Foundries.	ICTC	2018	DBLP DOI BibTeX RDF
29	Chia-Ping Tsai, Hung-Chang Hsiao, Yu-Chang Chao, Michael Hsu, Andy R. K. Chang	Bridging the Gap between Big Data System Software Stack and Applications: The Case of Semiconductor Wafer Fabrication Foundries.	IEEE BigData	2018	DBLP DOI BibTeX RDF
29	Victor Manuel Hernandez Bennetts, Erik Schaffernicht, Achim J. Lilienthal, Han Fan, Tomasz Piotr Kucner, Lena Andersson, Anders Johansson	Towards occupational health improvement in foundries through dense dust and pollution monitoring using a complementary approach with mobile and stationary sensing nodes.	IROS	2016	DBLP DOI BibTeX RDF
29	Gian Luigi Gragnani, Claudio Montecucco, Luca Casella	Active-RFID system operating in heavy environmental conditions to aid the production cycle of bentonite-coal dust mixtures for foundries.	ICMCS	2016	DBLP DOI BibTeX RDF
29	Vasily Bunakov, Tom Griffin, Brian Matthews, Stefano Cozzini	Metadata for Experiments in Nanoscience Foundries.	DAMDID/RCDL (Selected Papers)	2016	DBLP DOI BibTeX RDF
29	Cinzia Giannetti, Meghana R. Ransing, Rajesh S. Ransing, David C. Bould, David T. Gethin, Johann Sienz	Organisational Knowledge Management for Defect Reduction and Sustainable Development in Foundries.	Int. J. Knowl. Syst. Sci.	2015	DBLP DOI BibTeX RDF
29	Bernd Dreier, Florian Blas, Alexander Kostgeld	Data Acquisition in Cast Iron Foundries by Image Analysis.	VISAPP (3)	2015	DBLP DOI BibTeX RDF
29	Victor Claudio Bento de Camargo, Leandro Mattiolli, Franklina Maria Bragion Toledo	A knapsack problem as a tool to solve the production planning problem in small foundries.	Comput. Oper. Res.	2012	DBLP DOI BibTeX RDF
29	Javier Nieves, Igor Santos, Pablo García Bringas	Combination of Machine-Learning Algorithms for Fault Prediction in High-Precision Foundries.	DEXA (2)	2012	DBLP DOI BibTeX RDF
29	Rodolfo Florence Teixeira Jr., Flavio Cesar Faria Fernandes, Néocles Alves Pereira	Binary integer programming formulations for scheduling in market-driven foundries.	Comput. Ind. Eng.	2010	DBLP DOI BibTeX RDF
29	Silvio A. de Araujo, Marcos Nereu Arenales, Alistair R. Clark	Lot sizing and furnace scheduling in small foundries.	Comput. Oper. Res.	2008	DBLP DOI BibTeX RDF
29	Kazuhiko Terashima, Takanori Miyoshi, Yoshiyuki Noda	Innovative Automation Technologies and IT Applications of the Metal Casting Process Necessary for the Foundries of the 21st Century.	Int. J. Autom. Technol.	2008	DBLP DOI BibTeX RDF
29	Jamil Kawa, Yuhua Cheng, Hiroshi Iwai, Richard Goering, Michael Campbell, Raul Camposano, Jon Fields, Patrick Lin, Steve Lloyd, Joseph Sawicki, Ed Wan	Foundries, EDA vendors, and designers: who shoulders the blame when a design doesn't work in the nano-scale and wireless era?	CICC	2005	DBLP DOI BibTeX RDF
29	Jean-Michel Karam, Bernard Courtois, Hicham Boutamine	CAD Tools for Bridging Microsystems and Foundries.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
29	Martin Rüttgers	Design of a Method for Machine Scheduling for Core Blowers in Foundries.	Fuzzy Days	1997	DBLP DOI BibTeX RDF
29	Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, András Poppe, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner	CAD and Foundries for Microsystems.	DAC	1997	DBLP DOI BibTeX RDF
29	Jean-Michel Karam, Bernard Courtois, M. Bauge	High level CAD melds microsystems with foundries.	ED&TC	1996	DBLP DOI BibTeX RDF
16	Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger	Who solves the variability problem?	DAC	2010	DBLP DOI BibTeX RDF	IC variability
16	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
16	Michael Nelson 0002, Ani Nahapetian, Farinaz Koushanfar, Miodrag Potkonjak	SVD-Based Ghost Circuitry Detection.	Information Hiding	2009	DBLP DOI BibTeX RDF	Hardware Trojan horses, gate characterization, singular value decomposition, manufacturing variability
16	Lang Lin, Markus Kasper, Tim Güneysu, Christof Paar, Wayne P. Burleson	Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering.	CHES	2009	DBLP DOI BibTeX RDF	Trojan Hardware, Trojan Side-Channel, Hardware Trojan Detection, Covert Channel, Side-Channel Analysis
16	Miodrag Potkonjak, Ani Nahapetian, Michael Nelson 0002, Tammara Massey	Hardware Trojan horse detection using gate-level characterization.	DAC	2009	DBLP DOI BibTeX RDF	Hardware Trojan horses, gate-level characterization, linear programming, manufacturing variability
16	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Full-Chip Routing Considering Double-Via Insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Monica Figueiredo, Rui L. Aguiar	A Study on CMOS Time Uncertainty with Technology Scaling.	PATMOS	2008	DBLP DOI BibTeX RDF	Uncertainty, Noise, CMOS, Scaling, Jitter
16	Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov	EPIC: Ending Piracy of Integrated Circuits.	DATE	2008	DBLP DOI BibTeX RDF
16	Xiaoxiao Wang 0001, Mohammad Tehranipoor, Jim Plusquellic	Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions.	HOST	2008	DBLP DOI BibTeX RDF
16	Mainak Banga, Michael S. Hsiao	A Region Based Approach for the Identification of Hardware Trojans.	HOST	2008	DBLP DOI BibTeX RDF
16	Xiaoxiao Wang 0001, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic	Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.	DFT	2008	DBLP DOI BibTeX RDF
16	Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi	Quantified Impacts of Guardband Reduction on Design Process Outcomes.	ISQED	2008	DBLP DOI BibTeX RDF	Guardband, chip size, yield, runtime, wirelength, design iterations
16	Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh	DFM in practice: hit or hype?	DAC	2008	DBLP DOI BibTeX RDF	critical area analysis, CMP, yield, DFM, OPC, lithography
16	Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang	Novel wire density driven full-chip routing for CMP variation control.	ICCAD	2007	DBLP DOI BibTeX RDF
16	Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino	Locality-driven architectural cache sub-banking for leakage energy reduction.	ISLPED	2007	DBLP DOI BibTeX RDF	banked cache, memory hierarchy, leakage reduction, architectural optimization
16	Petter Solding, Patrik Thollander	Increased energy efficiency in a Swedish iron foundry through use of discrete event simulation.	WSC	2006	DBLP DOI BibTeX RDF
16	Lei-Ting Chen, David Lin, Dan Muuniz, Chia-Jiu Wang	Wafer Yield Estimation Using Support Vector Machines.	ISNN (2)	2006	DBLP DOI BibTeX RDF
16	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Impact of Gate-Length Biasing on Threshold-Voltage Selection.	ISQED	2006	DBLP DOI BibTeX RDF
16	Karen Chow	The Challenges and Impact of Parasitic Extraction at 65 nm.	ISQED	2006	DBLP DOI BibTeX RDF
16	Cheng-Wen Wu	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
16	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Novel full-chip gridless routing considering double-via insertion.	DAC	2006	DBLP DOI BibTeX RDF	redundant via insertion, routing, manufacturability
16	Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu	How will the fabless model survive?	DAC	2006	DBLP DOI BibTeX RDF	fabless, foundry, DFM, business
16	Jianwen Zhu, Fang Fang, Qianying Tang	Calligrapher: a new layout-migration engine for hard intellectual property libraries.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
16	Sean D. Cochrane, Keith Case, Robert I. M. Young, Jenny A. Harding, Samir Dani	Knowledge Sharing Between Design and Manufacture.	KES (4)	2005	DBLP DOI BibTeX RDF
16	Thomas L. Sterling	Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing.	NPC	2004	DBLP DOI BibTeX RDF
16	Fang Fang, Jianwen Zhu	Calligrapher: A New Layout Migration Engine Based on Geometric Closeness.	ISQED	2004	DBLP DOI BibTeX RDF
16	David Murfett	The Challenge of Testing RFID Integrated Circuits .	DELTA	2004	DBLP DOI BibTeX RDF
16	Keh-Jeng Chang	Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability.	IWSOC	2004	DBLP DOI BibTeX RDF
16	Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon	Were the good old days all that good?: EDA then and now.	DAC	2004	DBLP DOI BibTeX RDF
16	Antonio Luque Estepa, José Manuel Quero Reboul, C. Hibert, Philippe Flückiger	Fabrication process for a microfluidic valve.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
16	Kalyanmoy Deb, Abbadi Raji Reddy	Large-Scale Scheduling of Casting Sequences Using a Customized Genetic Algorithm.	Artificial Evolution	2003	DBLP DOI BibTeX RDF
16	Vipin Kumar, Franz-Josef Pfreundt, Hans Burkhard, José M. Laginha M. Palma	Applications on High Performance Computers.	Euro-Par	2002	DBLP DOI BibTeX RDF
16	Jennifer Blain Christen, Cristina E. Davis, Min Li, Andreas G. Andreou	Design, double sided post-processing, and packaging of CMOS compatible bio-MEMS device arrays.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
16	Daniel Ragan, Peter Sandborn, Paul Stoaks	A detailed cost model for concurrent use with hardware/software co-design.	DAC	2002	DBLP DOI BibTeX RDF	cost-performance trade-off, cost modeling
16	Shahid Masud, John V. McCanny	Design of Silicon IP Cores for Biorthogonal Wavelet Transforms.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	rapid design, FPGA, synthesis, system-on-a-chip, dsp
16	Medhat Karam, Wael Fikry, Hisham Haddara, Hani F. Ragai	Implementation of hot-carrier reliability simulation in Eldo.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
16	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne	Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design.	PATMOS	2000	DBLP DOI BibTeX RDF
16	John Kibarian	Ramping New IC Products in the Deep Submicron Age.	ISQED	2000	DBLP DOI BibTeX RDF
16	Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy	Survival strategies for mixed-signal systems-on-chip (panel session).	DAC	2000	DBLP DOI BibTeX RDF
16	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	Filling algorithms and analyses for layout density control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
16	Edoardo Charbon, Ilhami Torunoglu	Copyright protection of designs based on multi source IPs.	ICCAD	1999	DBLP DOI BibTeX RDF
16	Darko Kirovski, Miodrag Potkonjak	Localized watermarking: methodology and application to operation scheduling.	ICCAD	1999	DBLP DOI BibTeX RDF
16	Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky	Filling and slotting: analysis and algorithms.	ISPD	1998	DBLP DOI BibTeX RDF
16	A. Richard Newton	Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel).	DAC	1998	DBLP DOI BibTeX RDF
16	John P. Eurich	A tutorial introduction to the electronic design interchange format (tutorial session).	DAC	1986	DBLP DOI BibTeX RDF
16	John P. Gray, John Hunter	Portability in silicon CAE.	DAC	1985	DBLP DOI BibTeX RDF