Search results for "half-adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
105	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	The Half-Adder Form and Early Branch Condition Resolution.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction
81	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	Early Zero Detection.	ICCD	1996	DBLP DOI BibTeX RDF	half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP
43	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Quantum logic synthesis by symbolic reachability analysis.	DAC	2004	DBLP DOI BibTeX RDF	model checking, formal verification, quantum computing, satisfiability, reversible logic
37	los Roberto Mingoto Jr.	A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors.	ISMVL	2006	DBLP DOI BibTeX RDF
37	Dave A. Berque, Ian Serlin, Atanas Vlahov	A brief water excursion: introducing computer organization students to a water driven 1-bit half-adder.	ACM SIGCSE Bull.	2004	DBLP DOI BibTeX RDF	computer organization pedagogy, water-based computing
37	Hyoju Seo, Jungwon Lee, Hyelin Seok, Yongtae Kim	Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation.	ISOCC	2021	DBLP DOI BibTeX RDF
35	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Alejandro Giraldo-Quintero, Daniel Sierra-Sosa, Juan Guillermo Lalinde Pulido	Qiskit n-Bitstring Quantum Half-adder and Half-substractor.	ISSPIT	2020	DBLP DOI BibTeX RDF
33	Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder
24	Yonatan Pugachov, Moria Gulitski, Omri Mizrahi, Dror Malka	Design of All-Optical Logic Half-Adder Based on Photonic Crystal Multi-Ring Resonator.	Symmetry	2023	DBLP DOI BibTeX RDF
24	Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari, Alireza Asadi, Ehsan Mahmoodi	An ultra-low power and energy-efficient ternary Half-Adder based on unary operators and two ternary 3:1 multiplexers in 32-nm GNRFET technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
24	Keivan Saadi, Alireza Kashaninia, Reza Sabbaghi-Nadooshan	All-optical half adder based on triangular lattice photonic crystals with uniform structural parameters.	Photonic Netw. Commun.	2022	DBLP DOI BibTeX RDF
24	Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan	CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
24	Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri	CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
24	Abhay S. Vidhyadharan, Sanjay Vidhyadharan	An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
24	Sandip Swarnakar, Amrutha Guddati, Siva Koti Reddy, Ramanand Harijan, Santosh Kumar 0005	Performance analysis of optimized plasmonic half-adder circuit using Mach-Zehnder interferometer for high-speed switching applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
24	Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri	CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.	CoRR	2021	DBLP BibTeX RDF
24	Ramzi A. Jaber, Ahmad M. El-Hajj, Abdallah Kassem, Lina A. Nimri, Ali M. Haidar 0001	CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
24	Mohd Ziauddin Jahangir, J. Mounika	Design and simulation of an innovative CMOS ternary 3 to 1 multiplexer and the design of ternary half adder using ternary 3 to 1 multiplexer.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
24	Qi Wang 0070, Roman Verba, Thomas Brächer, Philipp Pirro, Andrii V. Chumak	Integrated magnonic half-adder.	CoRR	2019	DBLP BibTeX RDF
24	Mona Neisy, Mohammad Soroosh, Karim Ansari-Asl	All optical half adder based on photonic crystal resonant cavities.	Photonic Netw. Commun.	2018	DBLP DOI BibTeX RDF
24	Mohammad Reza Jalali-Azizpoor, Mohammad Soroosh, Yousef Seifi Kavian	Application of self-collimated beams in realizing all-optical photonic crystal-based half-adder.	Photonic Netw. Commun.	2018	DBLP DOI BibTeX RDF
24	Mohammad Mehdi Karkhanehchi, Fariborz Parandin, Abdulhamid Zahedi	Design of an all optical half-adder based on 2D photonic crystals.	Photonic Netw. Commun.	2017	DBLP DOI BibTeX RDF
24	Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi	A novel ternary half adder and multiplier based on carbon nanotube field effect transistors.	Frontiers Inf. Technol. Electron. Eng.	2017	DBLP DOI BibTeX RDF
24	Alex J. L. Morgan, David A. Barrow, Andrew Adamatzky, Martin M. Hanczyc	Simple fluidic digital half-adder.	CoRR	2016	DBLP BibTeX RDF
24	Kakali Datta, Debarka Mukhopadhyay, Paramartha Dutta	Design of a Logically Reversible Half Adder Using 2D 2-Dot 1-Electron QCA.	FICTA	2015	DBLP DOI BibTeX RDF
24	Bosheng Liu, Zhiqiang You, Xiangrao Li, Jishun Kuang, Zheng Qin	Comparator and half adder design using complementary resistive switches crossbar.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
24	Rekha Mehra, Shikha Jaiswal, H. K. Dixit	All optical half adder design based on semiconductor optical amplifier.	WOCN	2013	DBLP DOI BibTeX RDF
24	Sachin Lakra, T. V. Prasad 0001, Deepak Kumar Sharma, Shree Harsh Atrey, Anubhav Kumar Sharma	A Neuro-Fuzzy Technique for Implementing the Half-Adder Circuit Using the CANFIS Model	CoRR	2012	DBLP BibTeX RDF
21	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	E. Islas Pérez, Carlos A. Coello Coello, Arturo Hernández Aguirre, Alejandro Villavicencio Ramírez	Genetic Algorithms and Case-Based Reasoning as a Discovery and Learning Machine in the Optimization of Combinational Logic Circuits.	MICAI	2002	DBLP DOI BibTeX RDF
13	Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon	A dual band CMOS VCO with a balanced duty cycle buffer.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	dual band, VCO