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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 17 keywords
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Results
Found 32 publication records. Showing 32 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
105 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
The Half-Adder Form and Early Branch Condition Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 266-273, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction |
81 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
Early Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 545-, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP |
43 | William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski |
Quantum logic synthesis by symbolic reachability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 838-841, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
model checking, formal verification, quantum computing, satisfiability, reversible logic |
37 | los Roberto Mingoto Jr. |
A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 15, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Dave A. Berque, Ian Serlin, Atanas Vlahov |
A brief water excursion: introducing computer organization students to a water driven 1-bit half-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGCSE Bull. ![In: ACM SIGCSE Bull. 36(2), pp. 52-56, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
computer organization pedagogy, water-based computing |
37 | Hyoju Seo, Jungwon Lee, Hyelin Seok, Yongtae Kim |
Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 153-154, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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35 | Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis |
The circuit design of multiple-valued logic voltage-mode adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 162-165, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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35 | Alejandro Giraldo-Quintero, Daniel Sierra-Sosa, Juan Guillermo Lalinde Pulido |
Qiskit n-Bitstring Quantum Half-adder and Half-substractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSPIT ![In: IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2020, Louisville, KY, USA, December 9-11, 2020, pp. 1-10, 2020, IEEE, 978-1-6654-1589-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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33 | Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis |
Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 301-309, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
half-adder, VLSI MOS implementation, logic design, trees, codes, codes, adders, modular design, totally self-checking checkers, full-adder |
24 | Yonatan Pugachov, Moria Gulitski, Omri Mizrahi, Dror Malka |
Design of All-Optical Logic Half-Adder Based on Photonic Crystal Multi-Ring Resonator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 15(5), pp. 1063, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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24 | Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari, Alireza Asadi, Ehsan Mahmoodi |
An ultra-low power and energy-efficient ternary Half-Adder based on unary operators and two ternary 3:1 multiplexers in 32-nm GNRFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 51(10), pp. 4969-4983, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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24 | Keivan Saadi, Alireza Kashaninia, Reza Sabbaghi-Nadooshan |
All-optical half adder based on triangular lattice photonic crystals with uniform structural parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 43(3), pp. 204-211, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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24 | Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan |
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(8), pp. 4089-4105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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24 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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24 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 107, pp. 104961, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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24 | Sandip Swarnakar, Amrutha Guddati, Siva Koti Reddy, Ramanand Harijan, Santosh Kumar 0005 |
Performance analysis of optimized plasmonic half-adder circuit using Mach-Zehnder interferometer for high-speed switching applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 111, pp. 105040, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.02223, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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24 | Ramzi A. Jaber, Ahmad M. El-Hajj, Abdallah Kassem, Lina A. Nimri, Ali M. Haidar 0001 |
CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 96, pp. 104698, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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24 | Mohd Ziauddin Jahangir, J. Mounika |
Design and simulation of an innovative CMOS ternary 3 to 1 multiplexer and the design of ternary half adder using ternary 3 to 1 multiplexer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 90, pp. 82-87, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Qi Wang 0070, Roman Verba, Thomas Brächer, Philipp Pirro, Andrii V. Chumak |
Integrated magnonic half-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.02855, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
24 | Mona Neisy, Mohammad Soroosh, Karim Ansari-Asl |
All optical half adder based on photonic crystal resonant cavities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 35(2), pp. 245-250, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Reza Jalali-Azizpoor, Mohammad Soroosh, Yousef Seifi Kavian |
Application of self-collimated beams in realizing all-optical photonic crystal-based half-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 36(3), pp. 344-349, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Mehdi Karkhanehchi, Fariborz Parandin, Abdulhamid Zahedi |
Design of an all optical half-adder based on 2D photonic crystals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 33(2), pp. 159-165, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Sepehr Tabrizchi, Nooshin Azimi, Keivan Navi |
A novel ternary half adder and multiplier based on carbon nanotube field effect transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 18(3), pp. 423-433, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Alex J. L. Morgan, David A. Barrow, Andrew Adamatzky, Martin M. Hanczyc |
Simple fluidic digital half-adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1602.01084, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
24 | Kakali Datta, Debarka Mukhopadhyay, Paramartha Dutta |
Design of a Logically Reversible Half Adder Using 2D 2-Dot 1-Electron QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FICTA ![In: Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications, FICTA 2015, Durgapur, India, 16-18 November 2015., pp. 379-389, 2015, Springer, 978-81-322-2693-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Bosheng Liu, Zhiqiang You, Xiangrao Li, Jishun Kuang, Zheng Qin |
Comparator and half adder design using complementary resistive switches crossbar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 10(13), pp. 20130369, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Rekha Mehra, Shikha Jaiswal, H. K. Dixit |
All optical half adder design based on semiconductor optical amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOCN ![In: Tenth International Conference on Wireless and Optical Communications Networks, WOCN 2013, Bhopal, India, July 26-28, 2013, pp. 1-5, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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24 | Sachin Lakra, T. V. Prasad 0001, Deepak Kumar Sharma, Shree Harsh Atrey, Anubhav Kumar Sharma |
A Neuro-Fuzzy Technique for Implementing the Half-Adder Circuit Using the CANFIS Model ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1209.4895, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
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21 | William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski |
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1652-1663, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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21 | E. Islas Pérez, Carlos A. Coello Coello, Arturo Hernández Aguirre, Alejandro Villavicencio Ramírez |
Genetic Algorithms and Case-Based Reasoning as a Discovery and Learning Machine in the Optimization of Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI ![In: MICAI 2002: Advances in Artificial Intelligence, Second Mexican International Conference on Artificial Intelligence, Merida, Yucatan, Mexico, April 22-26, 2002, Proceedings, pp. 128-137, 2002, Springer, 3-540-43475-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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13 | Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon |
A dual band CMOS VCO with a balanced duty cycle buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 277-280, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dual band, VCO |
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