Search results for "hardware-acceleration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
86	David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic	On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	embedded systems, real-time, hardware acceleration, virtual prototyping, hardware/software co-design, LTE, DMA
40	Holger Scherl, Stefan Hoppe, Markus Kowarschik, Joachim Hornegger	Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging.	ICSE	2008	DBLP DOI BibTeX RDF	hardware abstraction layer, software design and architecture, parallel programming, patterns, medical imaging, hardware acceleration, 3-d reconstruction
40	H. Andrés Lagar-Cavilla, Niraj Tolia, Mahadev Satyanarayanan, Eyal de Lara	VMM-independent graphics acceleration.	VEE	2007	DBLP DOI BibTeX RDF	VMM-independence, virtualization, graphics, portability, hardware acceleration
37	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
37	Stephan Gatzka, Christian Hochberger	On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices.	HICSS	2005	DBLP DOI BibTeX RDF
35	Tse-Wei Chen 0001, Yi-Ling Chen 0008, Shao-Yi Chien	Photo Retrieval Based on Spatial Layout with Hardware Acceleration for Mobile Devices.	IEEE Trans. Mob. Comput.	2011	DBLP DOI BibTeX RDF	image segmentation, parallel processing, hardware acceleration, K-Means clustering, Photo retrieval
35	Stephen L. Smith 0002, Andrew J. Greensted, Jon Timmis	Hardware Acceleration of an Immune Network Inspired Evolutionary Algorithm for Medical Diagnosis.	ICES	2008	DBLP DOI BibTeX RDF	Parkinson’s disease, Evolutionary algorithm, Artificial immune systems, Hardware acceleration, Immune networks
35	Qinru Qiu, Daniel J. Burns, Prakash Mukre, Qing Wu 0002	Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword searching.	GECCO	2007	DBLP DOI BibTeX RDF	genetic algorithm, hardware acceleration, DNA
35	Chengyu Sun, Divyakant Agrawal, Amr El Abbadi	Hardware Acceleration for Spatial Selections and Joins.	SIGMOD Conference	2003	DBLP DOI BibTeX RDF	spatial selection, hardware acceleration, spatial join
35	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar	A fast, inexpensive and scalable hardware acceleration technique for functional simulation.	DAC	2002	DBLP DOI BibTeX RDF	FPGA, hardware acceleration, VLIW, functional simulation
35	Lisa M. Sobierajski, Ricardo S. Avila	A Hardware Acceleration Method for Volumetric Ray Tracing.	IEEE Visualization	1995	DBLP DOI BibTeX RDF	Volume Rendering, Ray Tracing, Hardware Acceleration
35	Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man	Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.	FPL	2002	DBLP DOI BibTeX RDF
32	Robert W. Horst	IP Storage and the CPU Consumption Myth.	NCA	2001	DBLP DOI BibTeX RDF
32	Bruno Zatt, Valter Ferreira, Luciano Volcan Agostini, Flávio Rech Wagner, Altamiro Amadeu Susin, Sergio Bampi	Motion Compensation Hardware Accelerator Architecture for H.264/AVC.	PSIVT	2007	DBLP DOI BibTeX RDF	MPEG-4 AVC, Video Coding, H.264/AVC, Motion Compensation, Hardware Acceleration
32	M. Ernst, Michael Jung 0002, Felix Madlener, Sorin A. Huss, Rainer Blümel	A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n).	CHES	2002	DBLP DOI BibTeX RDF	$ mathbb {GF}(2^n)$ arithmetic, Karatsuba multiplication, VHDL model generator, coprocessor synthesis, FPGA hardware acceleration, Atmel FPSLIC platform, Elliptic Curve cryptography
31	Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong-Min Kyung	Communication-efficient hardware acceleration for fast functional simulation.	DAC	2004	DBLP DOI BibTeX RDF	functional verification, communication overhead, simulation acceleration
29	Zhengdong Kang	Hardware acceleration of the SED algorithm for Biomolecular activity predictionBiomolecular activity algorithm (SED) uses FPGA parallel programmability to achieve hardware acceleration.	ISAIMS	2023	DBLP DOI BibTeX RDF
29	Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Thomas Lenart, Mats Gustafsson, Viktor Öwall	A Hardware Acceleration Platform for Digital Holographic Imaging.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose
25	Vassilis Dimopoulos, Giorgos Papadopoulos, Dionisios N. Pnevmatikatos	On the Importance of Header Classification in HW/SW Network Intrusion Detection Systems.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
25	Dionisis Chaikalis, Georgios Passalis, Nikos Sgouros, Dimitris Maroulis, Theoharis Theoharis	Hardware Acceleration for 3D Image Reconstruction.	Panhellenic Conference on Informatics	2008	DBLP DOI BibTeX RDF
25	David J. Lau, Orion Pritchard	Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions.	FPL	2006	DBLP DOI BibTeX RDF
25	Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk	Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.	DATE	2005	DBLP DOI BibTeX RDF
25	Philip M. Spira, Carl Hage	Hardware acceleration of gate array layout.	DAC	1985	DBLP DOI BibTeX RDF
23	Emilien Fournier	Accélération matérielle de la vérification de sûreté et vivacité sur des architectures reconfigurables. (Hardware acceleration of safety and liveness verification on reconfigurable architectures).		2022	RDF
23	Marco Pagani	Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA Computing Platforms. (Techniques pour l'amélioration de la prévisibilité de l'accélération matérielle pour les plateformes informatiques hétérogènes SoC-FPGA).		2020	RDF
23	Andrea Bocco	A variable precision hardware acceleration for scientific computing. (Une accélération matérielle à précision variable pour le calcul scientifique).		2020	RDF
23	Joël Cathébras	Hardware Acceleration for Homomorphic Encryption. (Accélération matérielle pour la cryptographie homomorphe).		2018	RDF
23	Maxime Legendre	Accélération algorithmique et matérielle des méthodes d'estimation de cartes d'abondances en imagerie hyperspectrale. (Algorithmic and hardware acceleration of abundance maps estimation methods in hyperspectral imaging).		2015	RDF
23	Kenneth L. Rice, Tarek M. Taha, Christopher N. Vutsinas	Scaling analysis of a neocortex inspired cognitive model on the Cray XD1.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Cognitive algorithms, Performance scaling, Parallel computing, Reconfigurable computing
23	Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang	A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition
23	Wenyin Fu, Katherine Compton	An execution environment for reconfigurable computing (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
22	Oskar Mencer	ASC: a stream compiler for computing with FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Imre Pechan, Béla Fehér	Molecular Docking on FPGA and GPU Platforms.	FPL	2011	DBLP DOI BibTeX RDF	FPGA vs, AutoDock, bioinformatics, GPU, hardware acceleration, molecular docking
21	Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman	Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DNA/protein sequence alignment, on-chip parallelism, bioinformatics, Network-on-chip, hardware acceleration
21	Ramin Mafi, Shahin Sirouspour, Behzad Mahdavikhah, Brian Moody, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici	A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies.	IEEE Trans. Haptics	2010	DBLP DOI BibTeX RDF	Object deformation, FPGA, parallel computing, haptics, finite element method, hardware acceleration, real-time simulation
21	Maxwell Walton, Gary Gréwal, Gerarda A. Darlington	Parallel FPGA-based implementation of scatter search.	GECCO	2010	DBLP DOI BibTeX RDF	0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search
21	René Müller 0001, Jens Teubner	FPGAs: a new point in the database design space.	EDBT	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, hardware acceleration, data processing
21	Ningyi Xu, Xiongfei Cai, Rui Gao, Lei Zhang 0001, Feng-Hsiung Hsu	FPGA Acceleration of RankBoost in Web Search Engines.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, hardware acceleration
21	Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt	Efficient memory management for hardware accelerated Java Virtual Machines.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Java Virtual Machine, hardware acceleration, Dynamic memory management
21	Xavier Llorà, Anusha Priya, Rohit Bhargava	Observer-invariant histopathology using genetics-based machine learning.	Nat. Comput.	2009	DBLP DOI BibTeX RDF	Observer-invariant histopathology, Vector instruction, MPI, Learning Classifier Systems, Hardware acceleration, Massive parallelism, Genetics-based machine learning, SSE2
21	Yotam Livny, Zvi Kogan, Jihad El-Sana	Seamless patches for GPU-based terrain rendering.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	Level-of-detail rendering, Hardware acceleration, Terrain visualization, View-dependent rendering
21	René Müller 0001, Jens Teubner	FPGA: what's in it for a database?	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	data processing vlsi, fpga, hardware acceleration
21	Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner	Memory-efficient distribution of regular expressions for fast deep packet inspection.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	regular expression, hardware acceleration, network intrusion detection, DFA, deep packet inspection
21	Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf	A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.	FCCM	2009	DBLP DOI BibTeX RDF	Machine Learning, FPGAs, Support Vector Machines, Parallel Architectures, Hardware Acceleration
21	Peter Bertels, Wim Heirman, Dirk Stroobandt	Strategies for dynamic memory allocation in hybrid architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	java, memory management, hardware acceleration
21	Yotam Livny, Michael Press, Jihad El-Sana	Interactive GPU-based adaptive cartoon-style rendering.	Vis. Comput.	2008	DBLP DOI BibTeX RDF	Cartoon rendering, Hardware acceleration, View-dependent rendering
21	Li Zhao 0002, Laxmi N. Bhuyan, Ravi R. Iyer 0001, Srihari Makineni, Donald Newell	Hardware Support for Accelerating Data Movement in Server Platform.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Copy engine, performance evaluation, TCP/IP, hardware acceleration, servers
21	Ove Daae Lampe, Ivan Viola, Nathalie Reuter, Helwig Hauser	Two-Level Approach to Efficient Visualization of Protein Dynamics.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	protein dynamics, hardware acceleration, Molecular visualization
21	Andrew Kinane, Noel E. O'Connor	Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	shape adaptive DCT/IDCT, low power, MPEG-4, hardware acceleration, video objects
21	José M. González, Vern Paxson, Nicholas Weaver	Shunting: a hardware/software architecture for flexible, high-performance network intrusion prevention.	CCS	2007	DBLP DOI BibTeX RDF	nips, fpga, intrusion detection, hardware acceleration, intrusion prevention, nids
21	Nicholas Weaver, Vern Paxson, José M. González	The shunt: an FPGA-based accelerator for network intrusion prevention.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, intrusion detection, hardware acceleration, NIC
21	Robert Cochran, Jay E. Steele	Second-order illumination in real-time (student paper).	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	GPU processing, global illumination, hardware acceleration, realtime rendering
21	Kin Fun Li, Darshika G. Perera	An Investigation of Chip-Level Hardware Support for Web Mining.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF	web mining, hardware acceleration, platform-based design, cosine similarity
21	Alfred R. Fuller, Harinarayan Krishnan, Karim Mahrous, Bernd Hamann, Kenneth I. Joy	Real-time procedural volumetric fire.	SI3D	2007	DBLP DOI BibTeX RDF	fire modeling, volume rendering, hardware acceleration, free-form deformation
21	Haitao Zhang, Arie E. Kaufman	Interactive Point-based Isosurface Exploration and High-quality Rendering.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	point-based visualization, hardware acceleration, Isosurface, isosurface extraction, GPU acceleration
21	Eric B. Lum, James Shearer, Kwan-Liu Ma	Interactive multi-scale exploration for volume classification.	Vis. Comput.	2006	DBLP DOI BibTeX RDF	Visualization, Classification, Volume rendering, Interface design, Hardware acceleration, Transfer functions, Filter banks, Scale-space filtering
21	Thomas Hübner, Yanci Zhang, Renato Pajarola	Multi-view point splatting.	GRAPHITE	2006	DBLP DOI BibTeX RDF	GPU processing, auto-stereoscopic visualization, multi-view rendering, hardware acceleration, point based rendering
21	Nathaniel Fout, Kwan-Liu Ma, James P. Ahrens	Time-varying, multivariate volume data reduction.	SAC	2005	DBLP DOI BibTeX RDF	compression, volume rendering, vector quantization, hardware acceleration, interactive visualization, time-varying data, multivariate data
21	GuangWei Zou, Xiang Liu	An Efficient Approach to Custom Instruction Set Generation.	RTCSA	2005	DBLP DOI BibTeX RDF	Major Block, Profiling, Hardware Acceleration, ASIPs, Custom Instruction
21	Daniel E. Laney, Steven P. Callahan, Nelson L. Max, Cláudio T. Silva, Steven Langer, Randall Frank	Hardware-Accelerated Simulated Radiography.	IEEE Visualization	2005	DBLP DOI BibTeX RDF	volume rendering, hardware acceleration
21	Iouliia Skliarova, António de Brito Ferrari	Reconfigurable Hardware SAT Solvers: A Survey of Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing, hardware acceleration, Boolean satisfiability
21	David M. Harris	An Exponentiation Unit for an OpenGL Lighting Engine.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	OpenGL hardware acceleration, table complexity, bipartite tables, Powering, computer arithmetic, table lookups, exponentiation
21	Xiaoming Wei, Ye Zhao 0004, Zhe Fan, Wei Li 0004, Feng Qiu, Suzanne Yoakum-Stover, Arie E. Kaufman	Lattice-Based Flow Field Modeling.	IEEE Trans. Vis. Comput. Graph.	2004	DBLP DOI BibTeX RDF	force evaluation, flow field interaction, two-way solid-fluid coupling, bubble simulation, feather simulation, computation on GPU, hardware acceleration, Lattice Boltzmann model
21	Marc Nienhaus, Jürgen Döllner	Sketchy drawings.	Afrigraph	2004	DBLP DOI BibTeX RDF	depth sprites, non-photorealistic rendering, sketching, real-time rendering, hardware-acceleration, image-space
21	Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.	FPGA	2004	DBLP DOI BibTeX RDF	finite-difference time-domain, FPGA, hardware acceleration, hardware implementation, FDTD
21	Wei Chen 0001, Liu Ren, Matthias Zwicker, Hanspeter Pfister	Hardware-Accelerated Adaptive EWA Volume Splatting.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	volume splatting, EWA filter, hardware acceleration, Direct volume rendering
21	Bartosz von Rymon-Lipinski, Nils Hanssen, Thomas Jansen 0005, Lutz Ritter, Erwin Keeve	Efficient Point-Based Isosurface Exploration Using the Span-Triangle.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	Point-Based Visualization, Visualization in Medicine, Hardware Acceleration, Isosurfaces, Large Data Set Visualization
21	Simon Stegmaier, Thomas Ertl	A Graphics Hardware-Based Vortex Detection and Visualization System.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	Features in Volume Data Sets, Flow Visualization, Hardware Acceleration, 3D Vector Field Visualization
21	Patrick S. McCormick, Jeff T. Inman, James P. Ahrens, Charles D. Hansen, Greg Roth	Scout: A Hardware-Accelerated System for Quantitatively Driven Visualization and Analysis.	IEEE Visualization	2004	DBLP DOI BibTeX RDF	volume rendering, hardware acceleration, Visualization systems, multivariate visualization
21	Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen 0001	Accelerating the secure remote password protocol using reconfigurable hardware.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	secure remote password protocol, authentication, WLAN, hardware acceleration, reconfigurable hardware, modular exponentiation
21	Daniel Weiskopf, Klaus Engel, Thomas Ertl	Interactive Clipping Techniques for Texture-Based Volume Visualization and Volume Shading.	IEEE Trans. Vis. Comput. Graph.	2003	DBLP DOI BibTeX RDF	Volume rendering, hardware acceleration, clipping, volume shading
21	Tommer Leyvand, Olga Sorkine, Daniel Cohen-Or	Ray space factorization for from-region visibility.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	line parameterization, visibility, hardware acceleration, PVS, occlusion culling, dual space
21	Huamin Qu, Feng Qiu, Nan Zhang 0011, Arie E. Kaufman, Ming Wan	Ray Tracing Height Fields.	Computer Graphics International	2003	DBLP DOI BibTeX RDF	ray tracing, hardware acceleration, terrain rendering, layered depth image, height field, depth image
21	Bong-Soo Sohn, Chandrajit L. Bajaj, Vinay Siddavanahalli	Feature based volumetric video compression for interactive playback.	VolVis	2002	DBLP DOI BibTeX RDF	isocontouring, time-varying volume visualization, wavelet transform, compression, hardware-acceleration
21	Kenneth E. Hoff III, Andrew Zaferakis, Ming C. Lin, Dinesh Manocha	Fast and simple 2D geometric proximity queries using graphics hardware.	SI3D	2001	DBLP DOI BibTeX RDF	graphics hardware acceleration, multi-pass techniques, collision detection, penetration depth, proximity queries
21	Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge	ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.	FCCM	1999	DBLP DOI BibTeX RDF	XPLA, compilers, static-analysis, computer-architecture, reconfigurable-computing, compiler-optimizations, hardware-acceleration, programmable-logic, CPLD, custom-instructions
21	Chia-Tien Dan Lo, Yi-Gang Tai	Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs.	ARC	2008	DBLP DOI BibTeX RDF
21	Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto	A novel SoC design methodology combining adaptive software and reconfigurable hardware.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Changsong Shen, Steve Oldridge, Sidney S. Fels	Open Source Vision Library (OpenVL) Based Local Positioning System.	AVSS	2006	DBLP DOI BibTeX RDF
21	Ronald Scrofano, Viktor K. Prasanna	Molecular dynamics - Preliminary investigation of advanced electrostatics in molecular dynamics on reconfigurable computers.	SC	2006	DBLP DOI BibTeX RDF	FPGA, reconfigurable, molecular dynamics, electrostatics
20	Andrea Damiani	On how to facilitate hardware acceleration of machine learning for non-experts in hardware design over the Edge, the Fog, and the Cloud		2023	RDF
20	Feng Shi 0006	Adaptive AI Algorithms for Generic Hardware and Unified Hardware Acceleration Architecture.		2021	RDF
20	Kris Min, Brenda Ly, Joshua Garner, Shahnam Mirzaei	A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware.	SoCC	2020	DBLP DOI BibTeX RDF
20	Farnoud Farahmand, Viet Ba Dang, Duc Tri Nguyen, Kris Gaj	Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign.	PQCrypto	2019	DBLP DOI BibTeX RDF
20	The H. Vu, Ryunosuke Murakami, Yuichi Okuyama 0001, Abderazek Ben Abdallah	Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro inspired Architecture in Hardware.	BigComp	2018	DBLP DOI BibTeX RDF
19	Weihang Zhu	A study of parallel evolution strategy: pattern search on a GPU computing platform.	GEC Summit	2009	DBLP DOI BibTeX RDF	evolutionary computations, GPU, evolution strategy, pattern search
18	Justin L. Tripp, Maya B. Gokhale, Anders A. Hansson	A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
18	Young-Il Kim, Chong-Min Kyung	Automatic translation of behavioral testbench for fully accelerated simulation.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Lin Shi, Hao Chen 0002, Jianhua Sun 0002	vCUDA: GPU accelerated high performance computing in virtual machines.	IPDPS	2009	DBLP DOI BibTeX RDF
17	Pavel Zemcík, Martin Zádník	AdaBoost Engine.	FPL	2007	DBLP DOI BibTeX RDF
17	Byeong Kil Lee, Lizy Kurian John, Eugene John	Architectural enhancements for network congestion control applications.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
17	Byeong Kil Lee, Lizy Kurian John, Eugene John	Architectural Support for Accelerating Congestion Control Applications in Network Processors.	ASAP	2005	DBLP DOI BibTeX RDF
16	Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede	Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.	CASES	2004	DBLP DOI BibTeX RDF	security, java, design, embedded systems, cryptography
15	E. Riegel, T. Indinger, Nikolaus A. Adams	Numerical simulation of fluid flow on complex geometries using the Lattice-Boltzmann method and CUDA-enabled GPUs.	SIGGRAPH Posters	2009	DBLP DOI BibTeX RDF
15	Radoslaw Mantiuk, Dawid Pajak	Acceleration of High Dynamic Range Imaging Pipeline Based on Multi-threading and SIMD Technologies.	ICCS (1)	2008	DBLP DOI BibTeX RDF	multi-threading architecture, computer visualization, image processing, high dynamic range imaging, SIMD architecture, SSE
15	Hao-Da Huang, Xin Tong 0001, Wen-Cheng Wang	Accelerated Parallel Texture Optimization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel, GPU, texture synthesis, flow visualization, energy minimization
15	Love Singhal, Elaheh Bozorgzadeh	Heterogeneous Floorplanner for FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
15	Jason D. Bakos	FPGA Acceleration of Gene Rearrangement Analysis.	FCCM	2007	DBLP DOI BibTeX RDF
15	Wencheng Wang, Feng Wei, Enhua Wu	View Dependent Sequential Point Trees.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	GPU, real time rendering, point-based rendering, visibility culling, view dependence