Results
Found 12 publication records. Showing 12 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Hitoshi Oi |
On the design of the local variable cache in a hardware translation-based java virtual machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 87-94, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hardware-translation, memory hierarchy, java virtual machine |
39 | Ramesh Radhakrishnan, Ravi Bhargava, Lizy Kurian John |
Improving Java performance using hardware translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 427-439, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Hitoshi Oi |
Instruction folding in a hardware-translation based java virtual machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 139-146, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware-translation, instruction folding, performance evaluation, java virtual machine |
31 | Xiangrong Zhou, Peter Petrov |
Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 33-38, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Xiangrong Zhou, Peter Petrov |
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 86-91, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 52(1), pp. 57-70, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
12 | Zi Yan, Guilherme Cox, Ján Veselý, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1701.07517, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
12 | Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 430-443, 2017, ACM, 978-1-4503-4892-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
12 | Hitoshi Oi |
Instruction Folding in a Hardware-Translation Based Java Virtual Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 10, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
12 | Hitoshi Oi |
Local variable access behavior of a hardware-translation based Java virtual machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Softw. ![In: J. Syst. Softw. 81(11), pp. 2059-2068, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang 0001 |
Processor Mechanisms for Software Shared Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 120-133, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
10 | Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni |
From Specification to Hardware Device: A Synthesis Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 5th International Conference on Formal Engineering Methods, ICFEM 2003, Singapore, November 5-7, 2003, Proceedings, pp. 665-681, 2003, Springer, 3-540-20461-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Rapid System Prototyping, Synthesis, Hardware Design |
Displaying result #1 - #12 of 12 (100 per page; Change: )
|