Search results for "incrementer"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
154	Bibhudatta Sahoo 0002, Keshab K. Parhi	A Low Power Correlator for CDMA Wireless Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	low-power, correlator, CDMA, incrementer
130	Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang	A high-speed CMOS incrementer/decrementer.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
117	Bibhudatta Sahoo 0002, Martin Kuhlmann, Keshab K. Parhi	A low-power correlator.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
47	Rolf Hakenes, Yiannos Manoli	A Segmented Gray Code for Low-Power Microcontroller Address Buses.	EUROMICRO	1999	DBLP DOI BibTeX RDF
47	Rolf Hakenes, Yiannos Manoli	Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter.	ICCD	1999	DBLP DOI BibTeX RDF
36	Chao Shang, Hongliang Li 0001, Fanman Meng, Qingbo Wu 0001, Heqian Qiu, Lanxiao Wang	Incrementer: Transformer for Class-Incremental Semantic Segmentation with Knowledge Distillation Focusing on Old Class.	CVPR	2023	DBLP DOI BibTeX RDF
36	Nuriddin Safoev, Jun-Cheol Jeon	Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
36	Dimitrios Balobas, Nikos Konofaos	High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS.	Integr.	2018	DBLP DOI BibTeX RDF
36	Jadav Chandra Das, Debashis De	Novel low power reversible binary incrementer design using quantum-dot cellular automata.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
36	M. Divya, Ritesh Belgudri, V. S. Kanchana Bhaaskaran	Design and analysis of program counter using finite state machine and incrementer based logic.	ICACCI	2014	DBLP DOI BibTeX RDF
36	Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang	Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
23	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
23	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Division Using Newton-Raphson Iteration.	ASAP	2004	DBLP DOI BibTeX RDF
23	Jean-Luc Rebourg, Jean-Denis Muller, Manuel Samuelides	SPIKE_4096: A Neural Integrated Circuit for Image Segmentation.	ICES	1998	DBLP DOI BibTeX RDF