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Publication years (Num. hits)
1987-2016 (14)
Publication types (Num. hits)
article(10) inproceedings(4)
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Found 14 publication records. Showing 14 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
36Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya Logical redundancies in irredundant combinational circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
36Neil Tennant Rule-Irredundancy and the Sequent Calculus for Core Logic. Search on Bibsonomy Notre Dame J. Formal Log. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
36Minghui Jiang 0001, Yong Zhang 0053 Parameterized complexity in multiple-interval graphs: Domination, partition, separation, irredundancy. Search on Bibsonomy Theor. Comput. Sci. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
36Minghui Jiang 0001, Yong Zhang 0053 Parameterized complexity in multiple-interval graphs: domination, partition, separation, irredundancy Search on Bibsonomy CoRR The full citation details ... 2011 DBLP  BibTeX  RDF
36Minghui Jiang 0001, Yong Zhang 0053 Parameterized Complexity in Multiple-Interval Graphs: Partition, Separation, Irredundancy. Search on Bibsonomy COCOON The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
36Chun-Chi Lin, Chun-Yao Wang Rewiring using IRredundancy Removal and Addition. Search on Bibsonomy DATE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Martin Charles Golumbic, Renu C. Laskar Irredundancy in Circular Arc Graphs. Search on Bibsonomy Discret. Appl. Math. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
36Edward R. Scheinerman Irredundancy in multiple interval representations. Search on Bibsonomy Discret. Math. The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
25Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler, Tiziano Villa Logic Minimization and Testability of 2-SPP Networks. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee RSYN: a system for automated synthesis of reliable multilevel circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
25Srinivas Devadas, Kurt Keutzer Validatable nonrobust delay-fault testable circuits via logic synthesis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Mikael Pettersson A Term Pattern-Match Compiler Inspired by Finite Automata Theory. Search on Bibsonomy CC The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Guozhu Dong, Rodney W. Topor Incremental Evaluation of Datalog Queries. Search on Bibsonomy ICDT The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang Multi-level logic minimization using implicit don't cares. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
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