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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 131 occurrences of 94 keywords
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Results
Found 92 publication records. Showing 92 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Shashank S. Nemawarkar, Guang R. Gao |
Latency Tolerance: A Metric for Performance Analysis of Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 227-232, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
performance analysis metric, multithreaded multiprocessor systems, tolerance index, program workload parameters, fine grain parallel program workloads, parallel architectures, multithreaded architectures, latency tolerance, closed queueing networks, analytical framework |
42 | Joan-Manuel Parcerisa, Antonio González 0001 |
Improving Latency Tolerance of Multithreading through Decoupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(10), pp. 1084-1094, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Access/execute decoupling, instruction-level parallelism, simultaneous multithreading, latency hiding, hardware complexity |
36 | Bo Liang, Hong An, Fang Lu, Rui Guo |
Improving Latency Tolerance of Network Processors Through Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 6th International Workshop, APPT 2005, Hong Kong, China, October 27-28, 2005, Proceedings, pp. 61-70, 2005, Springer, 3-540-29639-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Onur Mutlu, Hyesoon Kim, Yale N. Patt |
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(1), pp. 10-20, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
memory latency tolerance, processors, Runahead execution |
33 | Alvin R. Lebeck, Tong Li 0003, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan |
A Large, Fast Instruction Window for Tolerating Cache Misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 59-70, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Cache Memory, Memory Latency, Latency Tolerance, Instruction Window |
32 | Jarek Nieplocha, Vinod Tipparaju, Manojkumar Krishnan, Gopalakrishnan Santhanaraman, Dhabaleswar K. Panda 0001 |
Optimizing Mechanisms for Latency Tolerance in Remote Memory Access Communication on Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 1-4 December 2003, Kowloon, Hong Kong, China, pp. 138-147, 2003, IEEE Computer Society, 0-7695-2066-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Todd C. Mowry, Chi-Keung Luk |
Predicting Data Cache Misses in Non-Numeric Applications through Correlation Profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 314-320, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cache miss prediction, non-numeric applications, profiling, correlation, latency tolerance |
26 | Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu |
Tolerating Cache-Miss Latency with Multipass Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(1), pp. 40-47, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design |
24 | Raquel Pinto, Ricardo Bianchini, Claudio Luis de Amorim |
Comparing Latency-Tolerance Techniques for Software DSM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(11), pp. 1180-1190, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
performance, Distributed systems |
24 | Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen |
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 187-196, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song |
A simple latency tolerant processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 384-389, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Dongkeun Kim, Donald Yeung |
Design and evaluation of compiler algorithms for pre-execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002., pp. 159-170, 2002, ACM Press, 1-58113-574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Chen Ding, Ken Kennedy |
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 181-190, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
memory performance model, array reduction, store elimination, memory hierarchy, compiler optimizations, Memory bandwidth, loop fusion |
19 | Seif Haridi, Peter Van Roy, Per Brand, Michael Mehl, Ralf Scheidhauer, Gert Smolka |
Efficient logic variables for distributed computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 21(3), pp. 569-626, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Mozart, distributed algorithms, Oz |
18 | Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh |
On the potential of latency tolerant execution in speculative multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFMT ![In: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, IFMT 2008, Cairo, Egypt, November 24-25, 2008, pp. 3, 2008, ACM, 978-1-60558-407-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors |
18 | Dongkeun Kim, Donald Yeung |
A study of source-level compiler algorithms for automatic construction of pre-execution code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 22(3), pp. 326-379, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pre-execution, prefetch conversion, speculative loop parallelization, multithreading, program slicing, Data prefetching, memory-level parallelism |
18 | Andrew D. Hilton, Santosh Nagarakatte, Amir Roth |
iCFP: Tolerating All-Level Cache Misses in In-Order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(1), pp. 12-19, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
in-order processors, data cache misses, multithreaded execution, latency tolerance |
18 | Jacob Sorensen, Scott B. Baden |
Hiding Communication Latency with Non-SPMD, Graph-Based Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS (1) ![In: Computational Science - ICCS 2009, 9th International Conference, Baton Rouge, LA, USA, May 25-27, 2009, Proceedings, Part I, pp. 155-164, 2009, Springer, 978-3-642-01969-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
non-SPMD, coarse grain dataflow, parallel programming, latency tolerance |
18 | Parry Husbands, Katherine A. Yelick |
Multi-threading and one-sided communication in parallel LU factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, SC 2007, November 10-16, 2007, Reno, Nevada, USA, pp. 31, 2007, ACM Press, 978-1-59593-764-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multithreading, latency tolerance, dense linear algebra |
18 | Jordi Cortadella, Michael Kishinevsky, Bill Grundmann |
Synthesis of synchronous elastic architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 657-662, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
protocols, synthesis, latency-tolerance, latency-insensitive design |
18 | Michel Dubois 0001 |
Fighting the memory wall with assisted execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 168-180, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance |
18 | Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton |
Continual flow pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2004, Boston, MA, USA, October 7-13, 2004, pp. 107-119, 2004, ACM, 1-58113-804-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CFP, non-blocking, latency tolerance, instruction window |
18 | Thilo Kielmann, Henri E. Bal, Sergei Gorlatch |
Bandwidth-Efficient Collective Communication for Clustered Wide Area Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 492-499, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Models for Parallel Computers, Optimization, Grid Computing, Interconnection Networks, MPI, Performance Modeling, Cluster Computing, Runtime Support, Latency Tolerance |
18 | Peter Van Roy, Seif Haridi, Per Brand, Gert Smolka, Michael Mehl, Ralf Scheidhauer |
Mobile Objects in Distributed Oz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(5), pp. 804-851, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
network transparency, mobile objects, latency tolerance |
18 | William W. Pugh, Evan Rosser |
Iteration Space Slicing and Its Application to Communication Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 11th international conference on Supercomputing, ICS 1997, Vienna, Austria, July 7-11, 1997, pp. 221-228, 1997, ACM, 0-89791-902-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
message coalescing, program slicing, communication optimization, latency tolerance |
18 | Fredrik Dahlgren, Per Stenström |
Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(4), pp. 385-398, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Hardware-controlled prefetching, relaxed memory consistency, performance evaluation, shared-memory multiprocessors, latency tolerance |
18 | Luddy Harrison |
Examination of a Memory Access Classification Scheme for Pointer-Intensive and Numeric Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996, pp. 133-140, 1996, ACM, 0-89791-803-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CPU architecture, instruction profiling, memory access pattern classification, memory latency tolerance, data cache |
18 | Fredrik Dahlgren, Michel Dubois 0001, Per Stenström |
Sequential Hardware Prefetching in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(7), pp. 733-746, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Hardware-controlled prefetching, sequential prefetching, performance evaluation, shared-memory multiprocessors, memory consistency models, latency tolerance |
18 | John G. Cleary, Murray Pearson, Husam Kinawi |
The architecture of an optimistic CPU: the WarpEngine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 163-172, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory |
17 | Marcelo Orenes-Vera, Aninda Manocha, Jonathan Balkind, Fei Gao 0016, Juan L. Aragón, David Wentzlaff, Margaret Martonosi |
Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022, pp. 817-830, 2022, ACM, 978-1-4503-8610-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu |
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1804.11038, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
17 | Victor Eijkhout |
Task Graph Transformations for Latency Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1811.05077, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
17 | Akhil Arunkumar, Shin-Ying Lee, Vignesh Soundararajan, Carole-Jean Wu |
LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018, pp. 221-234, 2018, IEEE Computer Society, 978-1-5386-3659-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Sharanyan Srikanthan, Sandhya Dwarkadas, Kai Shen |
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Annual Technical Conference ![In: 2016 USENIX Annual Technical Conference, USENIX ATC 2016, Denver, CO, USA, June 22-24, 2016., pp. 323-336, 2016, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
17 | Youngsam Shin, Seok Joong Hwang, Jae Don Lee, Won-Jong Lee, Soojung Ryu |
Latency tolerance techniques for real-time ray tracing on mobile computing platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH Asia Mobile Graphics and Interactive Applications ![In: SIGGRAPH Asia 2015 Mobile Graphics and Interactive Applications, Kobe, Japan, November 2-6, 2015, pp. 1:1-1:4, 2015, ACM, 978-1-4503-3928-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
17 | Neal Clayton Crago, Omid Azizi, Steven S. Lumetta, Sanjay J. Patel |
Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 294-305, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
17 | David Alexander Munday |
Energy Efficient Memory Speculation With Memory Latency Tolerance Supporting Sequential Consistency Without A Coherence Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2013 |
RDF |
|
17 | Muhammad Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss |
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAPIDO ![In: Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '12, 23 January, 2012, Paris, France, pp. 1-8, 2012, ACM, 978-1-4503-1114-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Chien-Ping Lu, Brian Ko |
Latency tolerance for Throughput Computing: Designer track. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, pp. 524-525, 2012, ACM, 978-1-4577-1398-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
17 | Neal Clayton Crago |
Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2012 |
RDF |
|
17 | Neal Clayton Crago, Sanjay J. Patel |
OUTRIDER: efficient memory latency tolerance with decoupled strands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 117-128, 2011, ACM, 978-1-4503-0472-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Ashok Srinivasan, Namas Chandra |
Latency tolerance through parallelization of time in scientific applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Comput. ![In: Parallel Comput. 31(7), pp. 777-796, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton |
Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 24(6), pp. 62-73, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jarek Nieplocha, Vinod Tipparaju, Manojkumar Krishnan, Gopalakrishnan Santhanaraman, Dhabaleswar K. Panda 0001 |
Optimisation and performance evaluation of mechanisms for latency tolerance in remote memory access communication on clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Comput. Netw. ![In: Int. J. High Perform. Comput. Netw. 2(2/3/4), pp. 198-209, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Teemu Mäki-Patola, Perttu Hämäläinen |
Latency Tolerance for Gesture Controlled Continuous Sound Instrument without Tactile Feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMC ![In: Proceedings of the 2004 International Computer Music Conference, ICMC 2004, Miami, Florida, USA, November 1-6, 2004, 2004, Michigan Publishing. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Ashok Srinivasan, Namas Chandra |
Latency Tolerance through Parallelization of Time in Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Srikanth T. Srinivasan, Alvin R. Lebeck |
Load Latency Tolerance in Dynamically Scheduled Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 1, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
17 | Brian R. Fisk, R. Iris Bahar |
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 538-545, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Algorithms, Architecture, Caches |
17 | Srikanth T. Srinivasan, Alvin R. Lebeck |
Load Latency Tolerance in Dynamically Scheduled Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 148-159, 1998, ACM/IEEE Computer Society, 0-8186-8609-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Todd C. Mowry, Charles Q. C. Chan, Adley K. W. Lo |
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998, pp. 300-311, 1998, IEEE Computer Society, 0-8186-8323-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Charles Selvidge |
Compilation-based prefetching for memory latency tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1992 |
RDF |
|
16 | Huiyang Zhou |
A case for fault tolerance and performance enhancement using chip multi-processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 5(1), pp. 22-25, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Vijay S. Pai, Sarita V. Adve |
Comparing and Combining Read Miss Clustering and Software Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 292-303, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Costas Kyriacou, Paraskevas Evripidou |
Communication Assist for Data Driven Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Panhellenic Conference on Informatics ![In: Advances in Informatics, 8th Panhellenic Conference on Informatics, PCI 2001. Nicosia, Cyprus, November 8-10, 2001, Revised Selected Papers, pp. 351-367, 2001, Springer, 3-540-07544-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Youngsoo Shin, Kiyoung Choi |
Software synthesis through task decomposition by dependency analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 98-104, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CDFG, scheduler, dependency, C, VHDL, thread, Software synthesis |
15 | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt |
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 129-140, 2003, IEEE Computer Society, 0-7695-1871-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve |
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 218-226, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching |
15 | Joan-Manuel Parcerisa, Antonio González 0001 |
The Synergy of Multithreading and Access/Execute Decoupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 59-63, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Naraig Manjikian |
Combining Loop Fusion with Prefetching on Shared-memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 78-83, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Cache locality enhancement, Compilers, Prefetching, Shared-memory multiprocessors, Loop transformations |
15 | Koray Öner, Michel Dubois 0001 |
Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 7th international conference on Supercomputing, ICS 1993, Tokyo, Japan, July 20-22, 1993, pp. 338-347, 1993, ACM, 0-89791-600-X. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
SPARC |
11 | George Chin Jr., Andrès Márquez, Sutanay Choudhury, Kristyn J. Maschhoff |
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-9, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Farshad Ahdi, Vikram Srinivasan, Kee Chaing Chua |
Topology Control for Delay Sensitive Applications in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mob. Networks Appl. ![In: Mob. Networks Appl. 12(5-6), pp. 406-421, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
delay sensitive applications, wireless sensor networks, topology control |
11 | Gregory A. Koenig, Laxmikant V. Kalé |
Optimizing Distributed Application Performance Using Dynamic Grid Topology-Aware Load Balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-10, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Todd C. Mowry, Chi-Keung Luk |
Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(4), pp. 369-384, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cache miss prediction, correlation-based profiling, Cache performance |
11 | Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi |
Parallel Execution of Radix Sort Program Using Fine-Grain Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 136-145, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fine-grain communication, parallel radix sort, performance scalability, EM-X |
11 | Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi |
The EM-X Parallel Computer: Architecture and Basic Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 14-23, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
8 | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt |
Coordinated control of multiple prefetchers in multi-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 316-326, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
prefetching, multi-core, feedback control, memory systems |
8 | Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis |
Comparative evaluation of memory models for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(3), pp. 12:1-12:30, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations |
8 | Rajendra Singh, Peter Graham |
Performance Driven Partial Checkpoint/Migrate for LAM-MPI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: 22nd Annual International Symposium on High Performance Computing Systems and Applications (HPCS 2008), June 9-11, 2008, Québec City, Canada, pp. 110-116, 2008, IEEE Computer Society, 978-0-7695-3250-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Grids, MPI, Cluster Computing, Checkpoint, Migration |
8 | Kevin D. Kissell |
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 9-21, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Abhishek Das, William J. Dally |
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 405, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis |
Comparing memory systems for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 358-368, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches |
8 | Guangming Tan, Shengzhong Feng, Ninghui Sun |
Biology - Locality and parallelism optimization for dynamic programming algorithm in bioinformatics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 78, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallelism, dynamic programming, locality, tiling, cache-oblivious |
8 | Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August |
Automatic Thread Extraction with Decoupled Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 105-118, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Ashok Srinivasan, Yanan Yu, Namas Chandra |
Application of Reduce Order Modeling to Time Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2005, 12th International Conference, Goa, India, December 18-21, 2005, Proceedings, pp. 106-117, 2005, Springer, 3-540-30936-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Seungryul Choi, Nicholas Kohout, Sumit Pamnani, Dongkeun Kim, Donald Yeung |
A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 22(2), pp. 214-280, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory parallelism, pointer-chasing code, Data prefetching |
8 | Alfredo Cristóbal-Salas, Andrey Chernykh, Edelmira Rodríguez-Alcantar, Jean-Luc Gaudiot |
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFL ![In: Implementation and Application of Functional Languages, 16th International Workshop, IFL 2004, Lübeck, Germany, September 8-10, 2004, Revised Selected Papers, pp. 1-16, 2004, Springer, 3-540-26094-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Keita Teranishi, Padma Raghavan |
Parallel Hybrid Sparse Solvers Through Flexible Incomplete Cholesky Preconditioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing, State of the Art in Scientific Computing, 7th International Workshop, PARA 2004, Lyngby, Denmark, June 20-23, 2004, Revised Selected Papers, pp. 637-643, 2004, Springer, 3-540-29067-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Naohiko Shimizu, Ken Takatori |
A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 31(1), pp. 75-84, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Linux |
8 | Adeline Jacquet, Vincent Janot, Clement Leung, Guang R. Gao, Ramaswamy Govindarajan, Thomas L. Sterling |
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 268, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Chris R. Jesshope |
Multi-threaded Microprocessors - Evolution or Revolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 21-45, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Paramjit S. Oberoi, Gurindar S. Sohi |
Parallelism in the Front-End. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 230-240, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Jack J. Dongarra |
High Performance Computing, Computational Grid, and Numerical Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing Advanced Scientific Computing, 6th International Conference, PARA 2002, Espoo, Finland, June 15-18, 2002, Proceedings, pp. 35-36, 2002, Springer, 3-540-43786-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
8 | Amir Roth, Gurindar S. Sohi |
A quantitative framework for automated pre-execution thread selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 430-441, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
8 | James C. Phillips, Gengbin Zheng, Sameer Kumar 0001, Laxmikant V. Kalé |
NAMD: biomolecular simulation on thousands of processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, pp. 53:1-53:18, 2002, IEEE Computer Society, 0-7695-1524-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
8 | Nicholas Kohout, Seungryul Choi, Dongkeun Kim, Donald Yeung |
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 268-279, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | José Nelson Amaral, Guang R. Gao, Erturk Dogan Kocalar, Patrick O'Neill, Xinan Tang |
Design and Implementation of an Efficient Thread Partitioning Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 252-259, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
8 | Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi |
The Use of Multithreading for Exception Handling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 219-229, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
8 | Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh |
An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 39-50, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
8 | Fong Pong, Michel Dubois 0001 |
Formal Verification of Delayed Consistency Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 124-131, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
8 | Doug Burger, James R. Goodman, Alain Kägi |
Memory Bandwidth Limitations of Future Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 78-89, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
8 | Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, Donald Yeung |
The MIT Alewife Machine: Architecture and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 2-13, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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