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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 14 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
42 | Nabil Kerkiz, Amr Elchouemi, Don Bouldin |
Multi-FPGA Partitioning Method Based on Topological Levelization. |
J. Electr. Comput. Eng. |
2010 |
DBLP DOI BibTeX RDF |
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42 | Jong P. Yoon, Sungrim Kim |
Schema extraction and levelization for XML data. |
Data Mining and Knowledge Discovery: Theory, Tools, and Technology |
2001 |
DBLP DOI BibTeX RDF |
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36 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee |
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization |
26 | Pietro Babighian, Luca Benini, Enrico Macii |
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
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26 | I-De Huang, Sandeep K. Gupta 0001, Melvin A. Breuer |
Accurate and Efficient Static Timing Analysis with Crosstalk. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
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26 | Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli |
Techniques for crosstalk avoidance in the physical design of high-performance digital systems. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
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26 | Peter M. Maurer |
Two new techniques for unit-delay compiled simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
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