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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 253 occurrences of 163 keywords
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Results
Found 141 publication records. Showing 141 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Heiko Falk, Martin Schwarzer |
Loop Nest Splitting for WCET-Optimization and Predictability Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2006, October 26-27, 2006, Seoul, Korea, conjunction with CODES+ISSS 2006, pp. 115-120, 2006, IEEE Computer Society, 0-7803-9783-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
88 | Kathryn S. McKinley, Olivier Temam |
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 17(4), pp. 288-336, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
84 | Kathryn S. McKinley, Olivier Temam |
A Quantitative Analysis of Loop Nest Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996., pp. 94-104, 1996, ACM Press, 0-89791-767-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
73 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-Dimension Software Pipelining for Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 163-174, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Dorit Nuzman, Ayal Zaks |
Outer-loop vectorization: revisited for short SIMD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 2-11, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, data reuse, subword parallelism |
69 | Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao |
Single-dimension software pipelining for multidimensional loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 7, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Software pipelining, loop transformation, modulo scheduling |
65 | Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Analyzing data reuse for cache reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(4), pp. 851-876, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cache polymorphism, compilers, energy consumption, Embedded software, data reuse, cache locality |
65 | Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang 0002 |
Compiler-directed cache polymorphism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 165-174, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
cache polymorphism, compilers, energy consumption, embedded software, data reuse, cache locality |
65 | Waibhav Tembe, Santosh Pande |
Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(10), pp. 1269-1280, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded processors, data locality, program dependence graph, Loop fusion, limited memory |
65 | Lei Wang, Waibhav Tembe, Santosh Pande |
A Framework for Loop Distribution on Limited On-Chip Memory Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 9th International Conference, CC 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 141-156, 2000, Springer, 3-540-67263-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
65 | Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé |
Static and Dynamic Locality Optimizations Using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(9), pp. 922-941, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
cache miss estimation, compiler optimizations, integer linear programming, Data reuse, cache locality, memory layouts |
63 | Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski |
Impact of memory hierarchy on program partitioning and scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 93-102, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860 |
61 | Kalyan Muthukumar, Gautam Doshi |
Software Pipelining of Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 10th International Conference, CC 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 165-181, 2001, Springer, 3-540-41861-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
61 | Heiko Falk, Manish Verma |
Combined Data Partitioning and Loop Nest Splitting for Energy Consumption Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 8th International Workshop, SCOPES 2004, Amsterdam, The Netherlands, September 2-3, 2004, Proceedings, pp. 137-151, 2004, Springer, 3-540-23035-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Peiyi Tang, John N. Zigman |
Reducing data communication overhead for DOACROSS loop nests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 44-53, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
57 | Marta Jiménez, José M. Llabería, Agustín Fernández |
A Cost-Effective Implementation of Multilevel Tiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(10), pp. 1006-1020, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multilevel tiling, Compilers, memory hierarchy, loop transformations |
55 | Javed Absar, Min Li 0001, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor |
Locality optimization in wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 125-130, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
access, reuse, layout, spatial, temporal, loop-nest |
54 | Martin Griebl, Christian Lengauer |
On Scanning Space-Time Mapped While Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 677-688, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
while loop, parallelizing compilation, loop parallelization, space-time mapping |
54 | Michael E. Wolf, Monica S. Lam |
A Loop Transformation Theory and an Algorithm to Maximize Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 2(4), pp. 452-471, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
loop transformation theory, general loops, dependence vectors, lexicographically positive, compound transformations, coarsest fully permutable loop nests, fully permutable nests, parallel algorithm, parallel algorithms, parallel programming, heuristics, program compilers, precedence constraints, legality, code transformation, fine-grain parallelism, canonical form, wavefront, coarse grain parallelism, loop iterations, maximum degree |
51 | Christian Lengauer, Sergei Gorlatch, Christoph A. Herrmann |
The Static Parallelization of Loops and Recursions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 11(4), pp. 333-353, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
polytope model, parallelization, skeletons, divide-and-conquer, homomorphism, SPMD, higher-order function, loop nest |
51 | Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde |
On deriving data parallel code from a functional program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 766-772, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data parallel code, translation methodology, high level algorithmic specification, imperative data parallel language, applicative caching, compilation method, incremental transformations, compilation steps, loop nest generation, scheduling, formal specification, parallel programming, static analysis, partitioning, code generation, functional programming, functional program, program compilers, alignment, parallel languages, functional languages, program interpreters, abstract syntax tree, ALPHA |
50 | Tarek S. Abdelrahman, Naraig Manjikian, Gary Liu, Sudarsan Tandri |
Locality Enhancement for Large-Scale Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCR ![In: Languages, Compilers, and Run-Time Systems for Scalable Computers, 4th International Workshop, LCR '98, Pittsburgh, PA, USA, May 28-30, 1998, Selected Papers, pp. 335-342, 1998, Springer, 3-540-65172-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
50 | A. Allam, J. Ramanujam, Gerald Baumgartner, P. Sadayappan |
Memory minimization for tensor contractions using integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee |
A Layout-Conscious Iteration Space Transformation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(12), pp. 1321-1336, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
program optimization, loop transformations, Data reuse, cache locality, memory layouts |
50 | Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu 0001 |
Combined partitioning and data padding for scheduling multiple loop nests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 67-75, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
50 | Reinhard von Hanxleden, Ken Kennedy |
Relaxing SIMD Control Flow Constraints using Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), San Francisco, California, USA, June 17-19, 1992, pp. 188-199, 1992, ACM, 0-89791-475-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
FORTRAN |
46 | Guangyu Chen, Feihui Li, Mahmut T. Kandemir |
Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 163-174, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Sri Hari Krishna Narayanan |
A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 738-743, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scheduling and Partitioning, Compilers, Multiprocessor Systems |
46 | Sanghun Lee, Hirotomo Aso |
Loop-Synthesizing Transformation for Maintaining Parallelism and Enhancing Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 6-9 October 2003, Kaohsiung, Taiwan, pp. 156-163, 2003, IEEE Computer Society, 0-7695-2018-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Bob Blainey, Christopher Barton, José Nelson Amaral |
Removing Impediments to Loop Fusion Through Code Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 309-328, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam |
Morphable Cache Architectures: Potential Benefits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 128-137, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Martin Griebl, Christian Lengauer |
Classifying Loops for Space-Time Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. I ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume I, pp. 467-474, 1996, Springer, 3-540-61626-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer |
Optimizing Array-Intensive Applications for On-Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(5), pp. 396-411, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization |
42 | Yonghong Song, Rong Xu, Cheng Wang 0019, Zhiyuan Li 0001 |
Improving Data Locality by Array Contraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1073-1084, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
array contraction, loop shifting, optimization, performance, Compiler, memory, optimizing compilers, data locality |
42 | Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao |
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 175-188, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Min Zhao 0009, Bruce R. Childers, Mary Lou Soffa |
Predicting the impact of optimizations for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 1-11, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
code models, embedded systems, prediction, optimizing compilers, loop optimizations, resource models, optimization models |
42 | Mahmut T. Kandemir |
A compiler technique for improving whole-program locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of POPL 2001: The 28th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, London, UK, January 17-19, 2001, pp. 179-192, 2001, ACM, 1-58113-336-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
static optimizations, optimizing compilers, data reuse, cache locality, memory layouts |
42 | Agustín Fernández, José M. Llabería, Miguel Valero-García |
Loop Transformation Using Nonunimodular Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(8), pp. 832-840, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonunimodular transformations, loop transformations, linear transformations, Iteration space, unimodular transformations, Hermite Normal Form |
42 | Arun Kejariwal, Alexandru Nicolau, Hideki Saito 0001, Xinmin Tian, Milind Girkar, Utpal Banerjee, Constantine D. Polychronopoulos |
A general approach for partitioning N-dimensional parallel nested loops with conditionals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 49-58, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
partitioning, conditionals, parallel loops, affine, Fourier-Motzkin elimination |
38 | Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas |
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 301-321, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Memory architecture exploration, High level synthesis, Memory optimization, Multi-media, Code transformation |
38 | Siddhartha Chatterjee, Erin Parker, Philip J. Hanlon, Alvin R. Lebeck |
Exact Analysis of the Cache Behavior of Nested Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Snowbird, Utah, USA, June 20-22, 2001, pp. 286-297, 2001, ACM, 1-58113-414-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee |
A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 11th International Workshop, LCPC'98, Chapel Hill, NC, USA, August 7-9, 1998, Proceedings, pp. 34-50, 1998, Springer, 3-540-66426-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Jingling Xue, Qingguang Huang, Minyi Guo |
Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 34th International Conference on Parallel Processing (ICPP 2005), 14-17 June 2005, Oslo, Norway, pp. 107-115, 2005, IEEE Computer Society, 0-7695-2380-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | William W. Pugh, Evan Rosser |
Iteration Space Slicing for Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 12th International Workshop, LCPC'99, La Jolla/San Diego, CA, USA, August 4-6, 1999, Proceedings, pp. 164-184, 1999, Springer, 3-540-67858-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Qi Ning, Vincent Van Dongen, Guang R. Gao |
Automatic data and computation decomposition for distributed memory machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 103-112, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic data decomposition, automatic computation decomposition, compile-time technique, complex programs, perfect loop nests, nonperfect loop nests, loop-carried dependences, loop nest clusters, data locality constraint relaxation, homogeneous linear equations, hierarchical program nesting structures, nesting levels, compiler development, EPPP project, Environment for Portable Parallel Programming, computational complexity, parallel programming, parallelism, polynomial time algorithms, distributed memory systems, software portability, relaxation, distributed memory machines, program control structures, parallelising compilers, data redistributions, equations, data handling |
36 | Pierre-Yves Calland, Tanguy Risset |
Precise Tiling for Uniform Loop Nests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 330-, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
uniform dependence algorithm, convex cone, partitionning, tiling, loop nest |
34 | Yixin Shou, Robert van Engelen, Johnnie Birch |
Flow-Sensitive Loop-Variant Variable Classification in Linear Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers, pp. 323-337, 2007, Springer, 978-3-540-85260-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Nawaaz Ahmed, Nikolay Mateev, Keshav Pingali |
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 141-152, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 276-281, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
34 | Feihui Li, Mahmut T. Kandemir |
Locality-conscious workload assignment for array-based computations in MPSOC architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 95-100, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MPSoC, data locality |
33 | Marek Palkowski, Wlodzimierz Bielecki |
Parallel tiled Nussinov RNA folding loop nest generated using both dependence graph transitive closure and loop skewing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Bioinform. ![In: BMC Bioinform. 18(1), pp. 290, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
33 | Antonio Artés, Robert Fasthuber, José Luis Ayala, Praveen Raghavan, Francky Catthoor |
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 72(1), pp. 69-85, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
31 | Feihui Li, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy |
Exploiting last idle periods of links for network power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 134-137, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compiler, interconnection network, energy optimization |
31 | Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels |
Loop unrolling and shifting for reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 167-172, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau |
Control flow optimization in loops using interval analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 157-166, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algorithmic code transformation, compiler loop optimization, interval analysis |
31 | Nicolas Vasilache, Albert Cohen 0001, Louis-Noël Pouchet |
Automatic Correction of Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 292-304, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Lian Li 0002, Hui Wu 0001, Hui Feng, Jingling Xue |
Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 63-74, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye |
A Geometric Programming Framework for Optimal Multi-Level Tiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2004 Conference on High Performance Networking and Computing, 6-12 November 2004, Pittsburgh, PA, USA, CD-Rom, pp. 18, 2004, IEEE Computer Society, 0-7695-2153-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Byoungro So, Mary W. Hall, Pedro C. Diniz |
A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Berlin, Germany, June 17-19, 2002, pp. 165-176, 2002, ACM, 1-58113-463-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reuse analysis, design space exploration, loop transformations, data dependence analysis |
31 | Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Meenakshi A. Kandaswamy |
A Unified Framework for Optimizing Locality, Parallelism, and Communication in Out-of-Core Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(7), pp. 648-668, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
I/O-intensive codes, loop and data transformations, file layouts, optimizing compilers, out-of-core computations |
27 | Byoungro So, Mary W. Hall, Heidi E. Ziegler |
Custom Data Layout for Memory Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 291-302, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Albert Hartono, Muthu Manikandan Baskaran, Cédric Bastoul, Albert Cohen 0001, Sriram Krishnamoorthy, Boyana Norris, J. Ramanujam, P. Sadayappan |
Parametric multi-level tiling of imperfectly nested loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 147-157, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
imperfectly nested loops, parametric tiling |
27 | Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin |
MPSoC memory optimization for digital camera applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 424-427, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Timing Optimization of Nested Loops Considering Code Size for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 475-482, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Narasimhan Ramasubramanian, Ram Subramanian, Santosh Pande |
Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(1), pp. 45-66, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
operator parallelism, FPGAs, parallel computing, Compilers, loop transformation, reconfigurable systems |
27 | Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karaköy |
An energy saving strategy based on adaptive loop parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 195-200, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy consumption, multiprocessing, adaptive parallelization |
27 | Santosh Pande, Tareq Bali |
A Compilation Method for Communication-Efficient Partitioning of DOALL Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Compiler Optimizations for Scalable Parallel Systems Languages ![In: Compiler Optimizations for Scalable Parallel Systems Languages, Compilation Techniques, and Run Time Systems, pp. 413-444, 2001, Springer, 3-540-41945-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Sungdo Moon, Byoungro So, Mary W. Hall |
Evaluating Automatic Parallelization in SUIF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(1), pp. 36-49, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
array privatization, run-time parallelization, shared-memory multiprocessors, Parallelizing compilers, data dependence analysis |
27 | Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam |
Compiler Optimizations for I/O-Intensive Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 164-171, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Loop Parallelization: Revisiting Framework of Unimodular Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 420-428, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
linear loop transformations, nonlinear step, transformation process, maximum loop parallelism, perfect nested loops, tight recurrences, MIMD system, parallel algorithms, parallelizing algorithm, parallel programming, graph theory, dependence graph, loop parallelization, optimising compilers, coarse grain parallelism, unimodular transformations |
26 | Adhitha Dias, Logan Anderson, Kirshanthan Sundararajah, Artem Pelenitsyn, Milind Kulkarni 0001 |
SparseAuto: An Auto-Scheduler for Sparse Tensor Computations Using Recursive Loop Nest Restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2311.09549, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Adhitha Dias, Kirshanthan Sundararajah, Charitha Saumya, Milind Kulkarni 0001 |
SparseLNR: Accelerating Sparse Tensor Computations Using Loop Nest Restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.11622, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Adhitha Dias, Kirshanthan Sundararajah, Charitha Saumya, Milind Kulkarni 0001 |
SparseLNR: accelerating sparse tensor computations using loop nest restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28 - 30, 2022, pp. 15:1-15:14, 2022, ACM, 978-1-4503-9281-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Daniel Maier, Biagio Cosenza, Ben H. H. Juurlink |
ALONA: Automatic Loop Nest Approximation with Reconstruction and Space Pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2021: Parallel Processing - 27th International Conference on Parallel and Distributed Computing, Lisbon, Portugal, September 1-3, 2021, Proceedings, pp. 3-18, 2021, Springer, 978-3-030-85664-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Marek Palkowski, Wlodzimierz Bielecki |
Tiling Nussinov's RNA folding loop nest with a space-time approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Bioinform. ![In: BMC Bioinform. 20(1), pp. 208:1-208:11, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Jinyang Yao, Rongcai Zhao, Qi Wang, Xiaohan Tao |
Loop-nest Auto-vectorization Method Based on Benefit Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAIP ![In: Proceedings of the 2nd International Conference on Advances in Image Processing, ICAIP 2018, Chengdu, China, June 16-18, 2018, pp. 240-244, 2018, ACM, 978-1-4503-6460-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Wlodzimierz Bielecki, Marek Palkowski |
Transitive Closure Based Schedule of Loop Nest Statement Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACS ![In: Advances in Soft and Hard Computing, Proceedings of the International Conference on Advanced Computer Systems, ACS 2018, Miȩdzyzdroje, Poland, 24-26 September 2018., pp. 122-131, 2018, Springer, 978-3-030-03313-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Wlodzimierz Bielecki, Marek Palkowski |
Loop Nest Tiling for Image Processing and Communication Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACS ![In: Hard and Soft Computing for Artificial Intelligence, Multimedia and Security, Selected, Revised Papers from the International Conference on Advanced Computer Systems, ACS 2016, Miȩdzyzdroje, Poland, 19-21 October 2016., pp. 305-314, 2016, 978-3-319-48428-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Marek Palkowski, Tomasz Klimek, Wlodzimierz Bielecki |
TRACO: An automatic loop nest parallelizer for numerical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FedCSIS ![In: 2015 Federated Conference on Computer Science and Information Systems, FedCSIS 2015, Lódz, Poland, September 13-16, 2015, pp. 681-686, 2015, IEEE, 978-8-3608-1065-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
26 | Péter Arató, Gergely Suba |
A data flow graph generation method starting from c description by handling loop nest hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SACI ![In: 9th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2014, Timisoara, Romania, May 15-17, 2014, pp. 269-274, 2014, IEEE, 978-1-4799-4694-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Rachid Seghir, Vincent Loechner, Benoît Meister |
Integer affine transformations of parametric ℤ-polytopes and applications to loop nest optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 9(2), pp. 8:1-8:27, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
26 | |
Parallelization, Loop Nest. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Parallel Computing ![In: Encyclopedia of Parallel Computing, pp. 1458, 2011, Springer, 978-0-387-09765-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Utpal Banerjee |
Loop Nest Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Parallel Computing ![In: Encyclopedia of Parallel Computing, pp. 1068-1079, 2011, Springer, 978-0-387-09765-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Riyadh Baghdadi, Albert Cohen 0001, Cédric Bastoul, Louis-Noël Pouchet, Lawrence Rauchwerger |
The Potential of Synergistic Static, Dynamic and Speculative Loop Nest Optimizations for Automatic Parallelization ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1111.6756, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
26 | Vladimír Guzma, Teemu Pitkänen, Jarmo Takala |
Instruction buffer with limited control flow and loop nest support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XI, Samos, Greece, July 18-21, 2011, pp. 263-269, 2011, IEEE, 978-1-4577-0802-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
26 | Konrad Trifunovic, Dorit Nuzman, Albert Cohen 0001, Ayal Zaks, Ira Rosen |
Polyhedral-Model Guided Loop-Nest Auto-Vectorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: PACT 2009, Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, 12-16 September 2009, Raleigh, North Carolina, USA, pp. 327-337, 2009, IEEE Computer Society, 978-0-7695-3771-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Venkatesan Packirisamy, Antonia Zhai |
Exploiting TLS Parallelism at Multiple Loop-Nest Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 15th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2009, Shenzhen, China, December 8-11, 2009, pp. 205-212, 2009, IEEE Computer Society, 978-1-4244-5788-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | P. Jerry Martin, Clayton S. Ferner |
Suppressing Independent Loops in Packing/Unpacking Loop Nest to Reduce Message Size for Message-passing Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, Volume 1, pp. 98-104, 2007, CSREA Press, 1-60132-020-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
26 | Alban Douillet, Hongbo Rong, Guang R. Gao |
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 311-322, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Heiko Falk, Martin Schwarzer |
Loop Nest Splitting for WCET-Optimization and Predictability Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCET ![In: 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
26 | Rob F. Van der Wijngaart, Michael A. Frumkin |
Interference Lattice-based Loop Nest Tilings for Stencil Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSC ![In: Proceedings of the Tenth SIAM Conference on Parallel Processing for Scientific Computing, PPSC 2001, Portsmouth, Virginia, USA, March 12-14, 2001, 2001, SIAM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
26 | Alain Darte, Claude G. Diderich, Marc Gengler, Frédéric Vivien |
Scheduling the Computations of a Loop Nest with Respect to a Given Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 405-414, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Oh-Young Kwon, Gi-Ho Park, Tack-Don Han |
A compiler optimization to reduce execution time of loop nest. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 24(1), pp. 6-11, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Mohammed Fellahi, Albert Cohen 0001 |
Software Pipelining in Nested Loops with Prolog-Epilog Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 80-94, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen 0001, John Cavazos |
Iterative optimization in the polyhedral model: part ii, multidimensional time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, Tucson, AZ, USA, June 7-13, 2008, pp. 90-100, 2008, ACM, 978-1-59593-860-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
genetic algorithm, loop transformation, iterative compilation, affine scheduling |
23 | Chunhui Zhang, Fadi J. Kurdahi |
Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(1), pp. 63-98, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low power, DSP, memory hierarchy, tiling, data locality, iteration space |
23 | Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin |
MPSoC memory optimization using program transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 43, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, data cache, Data locality, compiler transformations |
23 | Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu |
Two-level tiling for MPSoC architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 314-319, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Johnnie Birch, Robert A. van Engelen, Kyle A. Gallivan, Yixin Shou |
An empirical evaluation of chains of recurrences for array dependence testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 295-304, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chains of recurrences, dependence testing, loop optimization |
23 | Evangelia Athanasaki, Kornilios Kourtis, Nikos Anastopoulos, Nectarios Koziris |
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Panhellenic Conference on Informatics ![In: Advances in Informatics, 10th Panhellenic Conference on Informatics, PCI 2005, Volos, Greece, November 11-13, 2005, Proceedings, pp. 600-610, 2005, Springer, 3-540-29673-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
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