Search results for "lowpower"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Sreejyothsna Ankam, N. Sudhakar Reddy	A mechanism to detecting flooding attacks in quantum enabled cloud-based lowpower and lossy networks.	Theor. Comput. Sci.	2023	DBLP DOI BibTeX RDF
36	Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham	Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style.	EMS	2013	DBLP DOI BibTeX RDF
36	Ilkka Hautala, Jani Boutellier, Jari Hannuksela	Programmable lowpower implementation of the HEVC Adaptive Loop Filter.	ICASSP	2013	DBLP DOI BibTeX RDF
36	Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen	Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology.	ICASSP	2011	DBLP DOI BibTeX RDF
36	Praveen K. Yenduri, Anna C. Gilbert, Michael P. Flynn, Shahrzad Naraghi	Rand PPM: A lowpower compressive sampling analog to digital converter.	ICASSP	2011	DBLP DOI BibTeX RDF
36	Konstantinos Anagnostopoulos, George Economakos	Lowpower design of multipliers using a full-adder isolation technique.	ICECS	2005	DBLP DOI BibTeX RDF
36	Ayuko Takagi, Kiyoshi Nishikawa, Hitoshi Kiya	Low-bit motion estimation with edge enhanced images for lowpower MPEG encoder.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
33	Finbarr O'Regan, Conor Heneghan	A Low Power Algorithm for Sparse System Identification using Cross-Correlation.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	sparse systems, low power digital signal processing, lowpower hardware, adaptive filter, system identification
33	Ravindra Jejurikar, Rajesh K. Gupta 0001	Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems.	ISLPED	2004	DBLP DOI BibTeX RDF	critical speed, lowpower, procrastication, resource standby energy, real-time systems, DVS, EDF scheduling
21	Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001	Towards Novel Approaches in Design Automation for FPGA Power Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF
21	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
21	Andrew B. Kahng, Sherief Reda, Puneet Sharma	On-Line Adjustable Buffering for Runtime Power Reduction.	ISQED	2007	DBLP DOI BibTeX RDF
21	Gaurav Mathur, Peter Desnoyers, Deepak Ganesan, Prashant J. Shenoy	Capsule: an energy-optimized object storage system for memory-constrained sensor devices.	SenSys	2006	DBLP DOI BibTeX RDF	sensor network, embedded systems, energy efficiency, file system, objects, flash memory, storage system
21	Wei Ye 0003, Fabio Silva, John S. Heidemann	Ultra-low duty cycle MAC with scheduled channel polling.	SenSys	2006	DBLP DOI BibTeX RDF	ultra-low duty cycle, scheduling, wireless sensor networks, energy efficiency, medium access control
21	Shi-lei Yan, Jian-wei Sun	Implementation and Optimization of H.264/AVC Encoder on Blackfin (ADSP-BF537) Processor.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
21	He Yan, Jianyun Hu, Li Qiang, Hao Min	Design of Low-power Baseband-processor for RFID Tag.	SAINT Workshops	2006	DBLP DOI BibTeX RDF
21	Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan	A scalable low power issue queue for large instruction window processors.	ICS	2006	DBLP DOI BibTeX RDF	complexity-effective architecture, wakeup logic, low-power architecture, issue logic
21	Wai-Chi Fang, Tsung-Hsien Lin	Low-Power Radio Design for Wireless Smart Sensor Networks.	IIH-MSP	2006	DBLP DOI BibTeX RDF
21	Praveen Parvathala	High Level Test Generation / SW based Embedded Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Fredkin/Toffoli Templates for Reversible Logic Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
21	Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel	Binding, Allocation and Floorplanning in Low Power High-Level Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
21	Trevor W. Fox, Alex Carreira, Laurence E. Turner	The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks.	IWSOC	2003	DBLP DOI BibTeX RDF
21	Josef Fenk, Peter Sehrig	Low-noise, low-voltage, low-power IF gain controlled amplifiers for wireless communication.	Wirel. Networks	1998	DBLP DOI BibTeX RDF
21	Enrico Macii, Massoud Pedram, Fabio Somenzi	High-Level Power Modeling, Estimation, and Optimization.	DAC	1997	DBLP DOI BibTeX RDF