Search results for "mesh-interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Anand Ganti, Thomas Tarman, Jason Wertz	Supercomputing interconnects.	WSC	2005	DBLP BibTeX RDF
28	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Amirhossein Shantia, Mohamed Ould-Khaoua	Evaluating the Performance of Adaptive Fault-Tolerant Routing Algorithms for Wormhole-Switched Mesh Interconnect Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
28	Farshad Safaei, Mahmood Fathy, Ahmad Khonsari, Mohamed Ould-Khaoua, Hosein Shafiei, S. Khosravipour	On Quantifying Fault Patterns of the Mesh Interconnect Networks.	AINA	2007	DBLP DOI BibTeX RDF
19	Yunseok Rhee, Joonwon Lee	A Scalable Cache Coherent Architecture for Large-Scale Mesh-Connected Multiprocessors.	ISPAN	1997	DBLP DOI BibTeX RDF	mesh-interconnect, directory-based protocol, multiprocessor, wormhole routing, cache coherence, dimension ordered routing
18	Junpeng Wan, Yanxiang Bi, Zhe Zhou 0001, Zhou Li 0001	Volcano: Stateless Cache Side-channel Attack by Exploiting Mesh Interconnect.	CoRR	2021	DBLP BibTeX RDF
18	Chia-Hsin Owen Chen, Sunghyun Park 0002, Suvinay Subramanian, Tushar Krishna, Bhavya K. Daya, Woo-Cheol Kwon, Brett Wilkerson, John Arends, Anantha P. Chandrakasan, Li-Shiuan Peh	SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect.	Hot Chips Symposium	2014	DBLP DOI BibTeX RDF
18	Roman Trobec	Evaluation of d-mesh Interconnect for SoC.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
18	Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook	TILE64 - Processor: A 64-Core SoC with Mesh Interconnect.	ISSCC	2008	DBLP DOI BibTeX RDF
18	Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar	A 5-GHz Mesh Interconnect for a Teraflops Processor.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnection fabric, network on chip, mesh, router, CMOS digital integrated circuits, crossbar
18	Stephan Bourduas, Zeljko Zilic	A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing.	NOCS	2007	DBLP DOI BibTeX RDF
18	Jacob Engel, Taskin Koçak	3D-Mesh Interconnect Architecture for Network Processors.	PDPTA	2005	DBLP BibTeX RDF
15	Renqiu Huang, Ranga Vemuri	Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs.	ISVLSI	2005	DBLP DOI BibTeX RDF
15	Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe	Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.	ASPLOS	1998	DBLP DOI BibTeX RDF
13	Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Mohamed Ould-Khaoua	Modeling and Predicting Point-to-Point Communication Delay of Circuit Switching in the Mesh-Connected Networks.	ICDCN	2008	DBLP DOI BibTeX RDF
9	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer 0001, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
9	Abhinav Bhatele, Laxmikant V. Kalé	Application-specific topology-aware mapping for three dimensional topologies.	IPDPS	2008	DBLP DOI BibTeX RDF