Search results for "micro-processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
34	Rami R. Razouk, Terri Stewart, Michael Wilson	Measuring Operating System Performance on Modern Micro-Processors.	SIGMETRICS	1986	DBLP DOI BibTeX RDF
25	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
23	Giovanni Squillero	MicroGP-An Evolutionary Assembly Program Generator.	Genet. Program. Evolvable Mach.	2005	DBLP DOI BibTeX RDF	micro-processors, assembly programs generation, evolutionary algorithms
23	Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
20	Gordon Bell	Future high performance computers.	ICS	1988	DBLP DOI BibTeX RDF
19	Lucanus J. Simonson, Lei He 0001	Micro-architecture Performance Estimation by Formula.	SAMOS	2005	DBLP DOI BibTeX RDF
19	S. Himavathi, B. Umamaheswari	Implementation of Nonlinear Fuzzy Models Using Microcontrollers.	AFSS	2002	DBLP DOI BibTeX RDF
16	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
16	Fazel Bateni, Robert W. Epps, Kameel Antami, Rokas Dargis, Jeffery A. Bennett, Kristofer G. Reyes, Milad Abolhasani	Autonomous Nanocrystal Doping by Self-Driving Fluidic Micro-Processors.	Adv. Intell. Syst.	2022	DBLP DOI BibTeX RDF
16	Fazel Bateni, Robert Epps, Kameel Abdel-Latif, Rokas Dargis, Jeffery A. Bennett, Kristofer G. Reyes, Milad Abolhasani	Autonomous Nanocrystal Doping by Self-Driving Fluidic Micro-Processors.	Adv. Intell. Syst.	2022	DBLP DOI BibTeX RDF
16	Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao	Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
16	Olav Lindtjorn, Robert G. Clapp, Oliver Pell, Oskar Mencer, Michael J. Flynn	Surviving the end of scaling of traditional micro processors in HPC.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
16	Jan Uerpmann	Challenges in the Design of Micro-Processors and other Integrated Circuits.	MBMV	2009	DBLP BibTeX RDF
16	Bertrand Granado, Lionel Lacassagne, Patrick Garda	Can General Purpose Micro-processors Simulate Neural Networks in Real-Time?	IWANN (2)	1999	DBLP DOI BibTeX RDF
14	Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi	How fast is an FPGA in image processing?	FPL	2008	DBLP DOI BibTeX RDF
13	Philipp Grabher, Johann Großschädl, Dan Page	Cryptographic Side-Channels from Low-Power Cache Memory.	IMACC	2007	DBLP DOI BibTeX RDF
11	Mianxiong Dong, Minyi Guo, Long Zheng 0001, Song Guo 0001	Performance Analysis of Resource Allocation Algorithms Using Cache Technology for Pervasive Computing System.	ICYCS	2008	DBLP DOI BibTeX RDF
11	Francisco J. Mesa-Martinez, Jose Renau	Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.	MICRO	2007	DBLP DOI BibTeX RDF
11	Fernando C. Colon, Robert M. Glorioso, Walter H. Kohler, Dominic W. Li	Coupling small computers for performance enhancement.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
8	Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker 0001	A System Architecture for Reconfigurable Trusted Platforms.	DATE	2008	DBLP DOI BibTeX RDF
8	ElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham	Using Model Trees for Computer Architecture Performance Analysis of Software Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	superscalar machine, computer architecture performance analysis, tuning software, statistical regression modeling, M5' algorithm, SPEC CPU2006 suite, performance model tree, prefetching, software application
8	Miroslav N. Velev	Comparison of schemes for encoding unobservability in translation to SAT.	ASP-DAC	2005	DBLP DOI BibTeX RDF
8	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner	Extreme Formal Modeling (XFM) for Hardware Models.	MTV	2004	DBLP DOI BibTeX RDF
8	Ralf Hoffmann, Matthias Korch, Thomas Rauber	Performance Evaluation of Task Pools Based on Hardware Synchronization.	SC	2004	DBLP DOI BibTeX RDF
8	Fabien Pelisson, Daniela Hall, Olivier Riff, James L. Crowley	Brand Identification Using Gaussian Derivative Histograms.	ICVS	2003	DBLP DOI BibTeX RDF	Probabilistic object recognition, histogram matching, invariant feature description
8	Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama	A Real-Time Visualization System for PIV.	FPL	2003	DBLP DOI BibTeX RDF
8	Lazaros Gymnopoulos, Stelios Dritsas, Stefanos Gritzalis, Costas Lambrinoudakis	GRID Security Review.	MMM-ACNS	2003	DBLP DOI BibTeX RDF
8	Ken Sakamura	Large Market on the Horizon.	IEEE Micro	2002	DBLP DOI BibTeX RDF
8	Eiji Tokunaga, Hiroo Ishikawa, Makoto Kurahashi, Yasunobu Morimoto, Tatsuo Nakajima	A Framework for Connecting Home Computing Middleware.	ICDCS Workshops	2002	DBLP DOI BibTeX RDF
8	Eric Goubault	Static Analyses of the Precision of Floating-Point Operations.	SAS	2001	DBLP DOI BibTeX RDF
8	Jan M. Rabaey, Marlene Wan	An Energy-Conscious Exploration Methodology for Reconfigurable DSPs.	DATE	1998	DBLP DOI BibTeX RDF
8	Dominique Lavenier, Yannick Saouter	Computing Goldbach Partitions Using Pseudo-random Bit Generator Operators on a FPFA Systolic Array.	FPL	1998	DBLP DOI BibTeX RDF
8	Werner Damm, Amir Pnueli, Sitvanit Ruah	Herbrand Automata for Hardware Verification.	CONCUR	1998	DBLP DOI BibTeX RDF
8	Janet Fabri	Automatic storage optimization.	SIGPLAN Symposium on Compiler Construction	1979	DBLP DOI BibTeX RDF
8	J. B. Harvill	Functional Parallelism in an Operand State Saving Computer.	Computer Architecture for Non-Numeric Processing	1978	DBLP DOI BibTeX RDF