Search results for "microinstructions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia	Micro embedded monitoring for security in application specific instruction-set processors.	CASES	2005	DBLP DOI BibTeX RDF	micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
50	Vicki H. Allan, Robert A. Mueller	Compaction with General Timing.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	general synchronous timing, microcode generation systems, branch delays, volatile registers, microoperations, multiple microinstructions, clocked microarchitectures, compilers, synchronisation, program compilers, microprogramming, target architecture, data-dependency graphs
39	Sunil R. Das, Amiya Nayak	A survey on bit dimension optimization strategies of microprograms.	MICRO	1990	DBLP BibTeX RDF
39	George W. Cox, William M. Corwin, Konrad K. Lai, Fred J. Pollack	A Unified Model and Implementation for Interprocess Communication in a Multiprocessor Environment.	SOSP	1981	DBLP DOI BibTeX RDF
39	M. Z. Al-Dahleh, I. M. Shehabat	A Method of Reduction of the Microinstructions of Synchronous Digital Systems.	J. Digit. Inf. Manag.	2007	DBLP BibTeX RDF
39	Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen	Run-time generation of HPS microinstructions from a VAX instruction stream.	MICRO	1986	DBLP DOI BibTeX RDF
39	Totadri Jayasri, Dhruba Basu	An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	maximal compatibility class, microinstruction organization, minimizing control store width, Linear programming, microprogramming
39	John F. Wakerly, Clifford R. Hollander, Daniel Davies	Placement of microinstructions in a two-dimensional address space.	MICRO (2)	1975	DBLP DOI BibTeX RDF
31	Gary E. Barnes	Comments on "The Identification of Maximal Parallelism in Straight-Line Microprograms".	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	straight-line microprograms, Horizontal microprograms, microinstructions, optimization, parallelism
19	Flavius Gruian, Mark Westmijze	Investigating hardware micro-instruction folding in a Java embedded processor.	JTRES	2010	DBLP DOI BibTeX RDF	BlueJEP, bytecode folding, embedded systems, Java processors, Bluespec
19	Roope Kaivola, Rajnish Ghughal, Naren Narasimhan, Amber Telfer, Jesse Whittemore, Sudhindra Pandav, Anna Slobodová, Christopher Taylor, Vladimir A. Frolov, Erik Reeber, Armaghan Naik	Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.	CAV	2009	DBLP DOI BibTeX RDF
19	Pedro Ángel Castillo Valdivieso, G. Fernández, Antonio Mora García, Juan Julián Merelo Guervós, José Luis Bernier, Alberto Prieto	Evolving machine microprograms.	GECCO	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
19	Pedro Ángel Castillo Valdivieso, G. Fernández, Juan Julián Merelo Guervós, José Luis Bernier, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Pablo García-Sánchez	Evolving Machine Microprograms: Application to the CODE2 Microarchitecture.	DCAI	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
19	Martin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, Hong Rao	An Array Control Unit for High Performance SIMD Arrays.	CAMP	2000	DBLP DOI BibTeX RDF	array control unit, high performance SIMD arrays, array utilization, SIMD arrays, parallel processing
19	Martin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy	Control for High-Speed PE Arrays.	ASAP	2000	DBLP DOI BibTeX RDF	Application Specific Array Processors, Array Control Unit, Parallel Architecture, SIMD processing
19	Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger	Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment.	HUG	1993	DBLP DOI BibTeX RDF
19	Srinivas Devadas, A. Richard Newton	Algorithms for hardware allocation in data path synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
19	Toshiaki Tanaka, Tsutomu Kobayashi, Osamu Karatsu	HARP: FORTRAN to silicon [compilation system].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
19	Sarma R. Vishnubhotla	A Microinstruction Based Procedure to Diagnose Hardware Failures in Industrial Robots.	Great Lakes Computer Science Conference	1989	DBLP DOI BibTeX RDF
19	K. Lall, J. William Atwood	A microprogrammed interpreter for concurrent Euclid.	MICRO	1989	DBLP DOI BibTeX RDF	Concurrent Euclid
19	Yap Siong Chua, Charles N. Winton	A Simulation Tool for Teaching CPU Design and Microprogramming Concepts.	APL	1989	DBLP DOI BibTeX RDF	APL
19	J. A. Chandross, H. V. Jagadish, Abhaya Asthana	The trap as a control flow mechanism.	MICRO	1988	DBLP BibTeX RDF
19	Onat Menzilcioglu	A case study in using two-level control stores.	MICRO	1987	DBLP DOI BibTeX RDF
19	Jayaram Bhasker, Tariq Samad	Compacting MIMOLA microcode.	MICRO	1987	DBLP DOI BibTeX RDF	clique partitioning, synthesis, compaction, microprogramming
19	Takanobu Baba, Hiroshi Minakawa, Kenzo Okuda	A visual microprogramming system.	MICRO	1987	DBLP DOI BibTeX RDF
19	Douglas W. Clark	Pipelining and Performance in the VAX 8800 Processor.	ASPLOS	1987	DBLP DOI BibTeX RDF	VAX
19	Thomas L. Boardman Jr.	A microprocessor architecture for digital device implementation.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF