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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 4 publication records. Showing 4 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope |
Supporting Microthread Scheduling and Synchronisation in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(4), pp. 343-381, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Microgrids, microthreads, schedulers, CMPs, register files |
42 | Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp |
Implementation and evaluation of a microthread architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 55(3), pp. 149-161, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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36 | Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz |
Difficult-Path Branch Prediction Using Subordinate Microthreads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 307-317, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high performance microprocessor, SSMT, microthread, branch prediction, microarchitecture, SMT, helper thread |
30 | Li Zhang 0034, Chris R. Jesshope |
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par Workshops ![In: Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007, Revised Selected Papers, pp. 38-48, 2007, Springer, 978-3-540-78472-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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