|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 14 occurrences of 13 keywords
|
|
|
Results
Found 23 publication records. Showing 23 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
61 | Benoît Dupont de Dinechin |
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2015 IEEE Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015, pp. 1-27, 2015, IEEE, 978-1-4673-8885-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
60 | Philip Top, Maya B. Gokhale |
Application Experiments: MPPA and FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 291-294, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Ambric, MPPA |
60 | Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis |
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings, pp. 141-148, 2009, IEEE Computer Society, 978-0-7695-3716-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MPPA, FPGA, Optical Flow, Reconfigurable Computing |
31 | Ganji Vasu, Mangipudi Sivakumar, Manyala Ramalinga Raju |
Optimal Model Approximation of Linear Time-Invariant Systems Using the Enhanced DE Algorithm and Improved MPPA Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(5), pp. 2376-2411, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
31 | Ganji Vasu, Mangipudi Sivakumar, Manyala Ramalinga Raju |
A novel model reduction approach for linear time-invariant systems via enhanced PSO-DV algorithm and improved MPPA method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Control. Eng. ![In: J. Syst. Control. Eng. 234(2), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
31 | Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge |
Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Perform. Evaluation ![In: Perform. Evaluation 143, pp. 102124, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
31 | Emmanuel Podestá Jr., Bruno Marques do Nascimento, Márcio Castro 0001 |
Energy Efficient Stencil Computations on the Low-Power Manycore MPPA-256 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2018: Parallel Processing - 24th International Conference on Parallel and Distributed Computing, Turin, Italy, August 27-31, 2018, Proceedings, pp. 642-655, 2018, Springer, 978-3-319-96982-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Masahiro Ishii 0002, Jérémie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa |
Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(12), pp. 2019-2030, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Rubén Salvador, Gustavo Marrero Callicó, Eduardo Juárez 0001, César Sanz |
Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017, Dresden, Germany, September 27-29, 2017, pp. 1-6, 2017, IEEE, 978-1-5386-3534-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Benoît Dupont de Dinechin, Amaury Graillat |
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AISTECS@HiPEAC ![In: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, pp. 35-40, 2017, ACM, 978-1-4503-5226-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
31 | Masahiro Ishii 0002, Jérémie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa |
Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2016, pp. 365, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
31 | Pierre-Edouard Beaucamps, Frédéric Blanc Kalray |
Demo: MPPA® manycore processor towards future ADAS system solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, October 12-14, 2016, pp. 243-244, 2016, IEEE, 979-1-0922-7915-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, Eduardo Juárez 0001, César Sanz |
Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASIP ![In: 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, October 12-14, 2016, pp. 154-160, 2016, IEEE, 979-1-0922-7915-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
31 | Minh Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert |
MPI communication on MPPA Many-core NoC: design, modeling and performance issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARCO ![In: Parallel Computing: On the Road to Exascale, Proceedings of the International Conference on Parallel Computing, ParCo 2015, 1-4 September 2015, Edinburgh, Scotland, UK, pp. 113-122, 2015, IOS Press, 978-1-61499-620-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
31 | Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert, Thierry Strudel |
A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCS ![In: Conceptual Structures for STEM Research and Education, 20th International Conference on Conceptual Structures, ICCS 2013, Mumbai, India, January 10-12, 2013. Proceedings, pp. 1654-1663, 2013, Springer, 978-3-642-35785-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
31 | David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis |
Rapid Synthesis and Simulation of Computational Circuits in an MPPA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 67(1), pp. 47-63, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
31 | Philip Top, Maya B. Gokhale |
Application Experiments: MPPA and FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA, pp. 126-135, 2009, CSREA Press, 1-60132-101-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
31 | Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis |
Comparing fine-grained performance on the Ambric MPPA against an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic, pp. 174-179, 2009, IEEE, 978-1-4244-3892-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis |
Rapid synthesis and simulation of computational circuits in an MPPA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009, pp. 151-158, 2009, IEEE Computer Society, 978-1-4244-4377-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Mike Butts |
Synchronization through Communication in a Massively Parallel Processor Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(5), pp. 32-40, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple data stream processors, synchronization, parallel architectures, multiprocessors, multicore architectures |
30 | Jessica Lin 0001, Michail Vlachos, Eamonn J. Keogh, Dimitrios Gunopulos, Jian-Wei Liu, Shou-Jian Yu, Jia-Jin Le |
A MPAA-Based Iterative Clustering Algorithm Augmented by Nearest Neighbors Search for Time-Series Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PAKDD ![In: Advances in Knowledge Discovery and Data Mining, 9th Pacific-Asia Conference, PAKDD 2005, Hanoi, Vietnam, May 18-20, 2005, Proceedings, pp. 333-342, 2005, Springer, 3-540-26076-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Blake C. Mason, Dipak Ghosal, Cherita L. Corbett |
Evaluation of a Massively Parallel Architecture for Network Security Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 85-91, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Massively Parallelized Processing Architecture (MPPA), Ambric, entropy function, malware detection, experimental analysis, covert timing channel |
29 | David B. Thomas, Lee W. Howes, Wayne Luk |
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 63-72, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mppa, fpga, monte-carlo, random numbers, gpu |
Displaying result #1 - #23 of 23 (100 per page; Change: )
|
|