Search results for "mppa"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
61	Benoît Dupont de Dinechin	Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor.	Hot Chips Symposium	2015	DBLP DOI BibTeX RDF
60	Philip Top, Maya B. Gokhale	Application Experiments: MPPA and FPGA.	FCCM	2009	DBLP DOI BibTeX RDF	Ambric, MPPA
60	Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis	Optical Flow on the Ambric Massively Parallel Processor Array (MPPA).	FCCM	2009	DBLP DOI BibTeX RDF	MPPA, FPGA, Optical Flow, Reconfigurable Computing
31	Ganji Vasu, Mangipudi Sivakumar, Manyala Ramalinga Raju	Optimal Model Approximation of Linear Time-Invariant Systems Using the Enhanced DE Algorithm and Improved MPPA Method.	Circuits Syst. Signal Process.	2020	DBLP DOI BibTeX RDF
31	Ganji Vasu, Mangipudi Sivakumar, Manyala Ramalinga Raju	A novel model reduction approach for linear time-invariant systems via enhanced PSO-DV algorithm and improved MPPA method.	J. Syst. Control. Eng.	2020	DBLP DOI BibTeX RDF
31	Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge	Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks.	Perform. Evaluation	2020	DBLP DOI BibTeX RDF
31	Emmanuel Podestá Jr., Bruno Marques do Nascimento, Márcio Castro 0001	Energy Efficient Stencil Computations on the Low-Power Manycore MPPA-256 Processor.	Euro-Par	2018	DBLP DOI BibTeX RDF
31	Masahiro Ishii 0002, Jérémie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa	Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
31	Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Rubén Salvador, Gustavo Marrero Callicó, Eduardo Juárez 0001, César Sanz	Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier.	DASIP	2017	DBLP DOI BibTeX RDF
31	Benoît Dupont de Dinechin, Amaury Graillat	Network-on-chip service guarantees on the kalray MPPA-256 bostan processor.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
31	Masahiro Ishii 0002, Jérémie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa	Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM.	IACR Cryptol. ePrint Arch.	2016	DBLP BibTeX RDF
31	Pierre-Edouard Beaucamps, Frédéric Blanc Kalray	Demo: MPPA® manycore processor towards future ADAS system solutions.	DASIP	2016	DBLP DOI BibTeX RDF
31	Daniel Madroñal, Raquel Lazcano, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, Eduardo Juárez 0001, César Sanz	Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platform.	DASIP	2016	DBLP DOI BibTeX RDF
31	Minh Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert	MPI communication on MPPA Many-core NoC: design, modeling and performance issues.	PARCO	2015	DBLP DOI BibTeX RDF
31	Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert, Thierry Strudel	A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor.	ICCS	2013	DBLP DOI BibTeX RDF
31	David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis	Rapid Synthesis and Simulation of Computational Circuits in an MPPA.	J. Signal Process. Syst.	2012	DBLP DOI BibTeX RDF
31	Philip Top, Maya B. Gokhale	Application Experiments: MPPA and FPGA.	ERSA	2009	DBLP BibTeX RDF
31	Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis	Comparing fine-grained performance on the Ambric MPPA against an FPGA.	FPL	2009	DBLP DOI BibTeX RDF
31	David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis	Rapid synthesis and simulation of computational circuits in an MPPA.	FPT	2009	DBLP DOI BibTeX RDF
30	Mike Butts	Synchronization through Communication in a Massively Parallel Processor Array.	IEEE Micro	2007	DBLP DOI BibTeX RDF	multiple data stream processors, synchronization, parallel architectures, multiprocessors, multicore architectures
30	Jessica Lin 0001, Michail Vlachos, Eamonn J. Keogh, Dimitrios Gunopulos, Jian-Wei Liu, Shou-Jian Yu, Jia-Jin Le	A MPAA-Based Iterative Clustering Algorithm Augmented by Nearest Neighbors Search for Time-Series Data Streams.	PAKDD	2005	DBLP DOI BibTeX RDF
29	Blake C. Mason, Dipak Ghosal, Cherita L. Corbett	Evaluation of a Massively Parallel Architecture for Network Security Applications.	PDP	2010	DBLP DOI BibTeX RDF	Massively Parallelized Processing Architecture (MPPA), Ambric, entropy function, malware detection, experimental analysis, covert timing channel
29	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu