Search results for "page-mode"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
81	Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu	Processor Directed Dynamic Page Policy.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Godson-2, Memory Control Policy, Dynamic Page Policy, Open Page, Close Page
28	Amer Diwan, David Tarditi, J. Eliot B. Moss	Memory System Performance of Programs with Intensive Heap Allocation	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	automatic storage reclamation, copying garbage collection, heap allocation, page mode, subblock placement, write through, write-back, write-miss policy, garbage collection, generational garbage collection, write-policy, write-buffer
26	Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John	Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.	MICRO	2011	DBLP DOI BibTeX RDF
25	Yoonseo Choi, Taewhan Kim, Hwansoo Han	Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
25	Yoonseo Choi, Taewhan Kim	Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.	DAC	2003	DBLP DOI BibTeX RDF	page/burst modes, embedded system, memory layout, storage assignment
21	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
16	Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge	Rethinking DRAM's Page Mode With STT-MRAM.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
16	Muhammad M. Rafique, Zhichun Zhu	Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM.	IEEE Trans. Parallel Distributed Syst.	2021	DBLP DOI BibTeX RDF
16	Yimo Du, Youtao Zhang, Nong Xiao	Dual-Page Mode: Exploring Parallelism in MLC Flash SSDs.	HPCC/CSS/ICESS	2014	DBLP DOI BibTeX RDF
16	Steven A. Moyer, William A. Wulf	Modeling Optimal Effective Bandwidth of Page-Mode Memory for Stream-Oriented Computations.	J. Complex.	1994	DBLP DOI BibTeX RDF
16	T. A. Peelen, Ad J. van de Goor	Using the page mode of dynamic RAMs to obtain a pseudo cache.	Microprocess. Microsystems	1987	DBLP DOI BibTeX RDF
12	Liuxi Yang, Josep Torrellas	Speeding up the Memory Hierarchy in Flat COMA Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	cache-only memory architectures, cache coherence protocols, cache hierarchies, scalable shared-memory multiprocessors
11	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Incorporating DRAM access modes into high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
11	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
8	Jason F. Cantin, Mikko H. Lipasti, James E. Smith 0001	Stealth prefetching.	ASPLOS	2006	DBLP DOI BibTeX RDF	multiprocessors, prefetching, coherence
8	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
8	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
8	Betty Prince	A Tribute to Graphics Drams.	MTDT	1999	DBLP DOI BibTeX RDF
8	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	A Performance Comparison of Contemporary DRAM Architectures.	ISCA	1999	DBLP DOI BibTeX RDF