Search results for "register-exchange"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
38	Yun-Nan Chang	An Efficient In-Place VLSI Architecture for Viterbi Algorithm.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	register-exchange, trace-back, ACS unit, Viterbi decoder
38	D. A. F. Ei-Dib, Mohamed I. Elmasry	Low-power register-exchange Viterbi decoder for high-speed wireless communications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
28	Jae-Sun Han, Tae-Jin Kim, Chanho Lee	High performance Viterbi decoder using modified register exchange methods.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
28	Stefan R. Meier, Mario Steinert, Steffen Buch	Testability of path history memories with register-exchange architecture used in Viterbi-decoders.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
23	Chang-Jin Choi, Sang-Hun Yoon, Jong-Wha Chong, Shouyin Liu	A New Low-Power and High Speed Viterbi Decoder Architecture.	ICUCT	2006	DBLP DOI BibTeX RDF	RE-exchange, low-power, look-ahead, viterbi
19	Anil Kumar, V. Ravichandran, S. Sudhakar	A Novel Approach for FPGA Implementation of Register Exchange Based Viterbi Decoder and Re-Encoding based Node Synchronizer.	ANTS	2019	DBLP DOI BibTeX RDF
19	Yong Chen 0014, Emil Matús, Gerhard P. Fettweis	Register-Exchange Based Connection Allocator for Circuit Switching NoCs.	PDP	2017	DBLP DOI BibTeX RDF
19	D. M. Khatri, S. L. Haridas	Soft output Viterbi decoder using hybrid register exchange.	ICWET	2011	DBLP DOI BibTeX RDF
19	S. L. Haridas, N. K. Choudhari	Design of Viterbi decoder with minimum transition hybrid register exchange processing.	ICWET	2010	DBLP DOI BibTeX RDF
19	Ming-Der Shieh, Tai-Ping Wang, Der-Wei Yang	Low-power register-exchange survivor memory architectures for Viterbi decoders.	IET Circuits Devices Syst.	2009	DBLP DOI BibTeX RDF
19	Matthias Kamuf, Viktor Öwall, John B. Anderson	Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
19	Dalia A. El-Dib, Mohamed I. Elmasry	Modified register-exchange Viterbi decoder for low-power wireless communications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
17	Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre	Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	wireless LAN, OFDM, viterbi
17	Fei Sun, Tong Zhang 0002	Parallel high-throughput limited search trellis decoder VLSI design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
17	Yun-Nan Chang	Design of soft-output Viterbi decoders with hybrid trace-back processing.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
9	Robert Cypher, C. Bernard Shung	Generalized trace-back techniques for survivor memory management in the Viterbi algorithm.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF	trace-back, survivor memory, VLSI area requirements, Viterbi algorithm