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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 7 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
38 | Yun-Nan Chang |
An Efficient In-Place VLSI Architecture for Viterbi Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(3), pp. 317-324, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
register-exchange, trace-back, ACS unit, Viterbi decoder |
38 | D. A. F. Ei-Dib, Mohamed I. Elmasry |
Low-power register-exchange Viterbi decoder for high-speed wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 737-740, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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28 | Jae-Sun Han, Tae-Jin Kim, Chanho Lee |
High performance Viterbi decoder using modified register exchange methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 553-556, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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28 | Stefan R. Meier, Mario Steinert, Steffen Buch |
Testability of path history memories with register-exchange architecture used in Viterbi-decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 165-168, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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23 | Chang-Jin Choi, Sang-Hun Yoon, Jong-Wha Chong, Shouyin Liu |
A New Low-Power and High Speed Viterbi Decoder Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUCT ![In: Ubiquitous Convergence Technology, First International Conference, ICUCT 2006, Jeju Island, Korea, December 5-6, 2006, Revised Selected Papers, pp. 283-291, 2006, Springer, 978-3-540-71788-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RE-exchange, low-power, look-ahead, viterbi |
19 | Anil Kumar, V. Ravichandran, S. Sudhakar |
A Novel Approach for FPGA Implementation of Register Exchange Based Viterbi Decoder and Re-Encoding based Node Synchronizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANTS ![In: 2019 IEEE International Conference on Advanced Networks and Telecommunications Systems, ANTS 2019, Goa, India, December 16-19, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-3715-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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19 | Yong Chen 0014, Emil Matús, Gerhard P. Fettweis |
Register-Exchange Based Connection Allocator for Circuit Switching NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2017, St. Petersburg, Russia, March 6-8, 2017, pp. 559-566, 2017, IEEE Computer Society, 978-1-5090-6058-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
19 | D. M. Khatri, S. L. Haridas |
Soft output Viterbi decoder using hybrid register exchange. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25 - 26, 2011, pp. 942-945, 2011, ACM, 978-1-4503-0449-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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19 | S. L. Haridas, N. K. Choudhari |
Design of Viterbi decoder with minimum transition hybrid register exchange processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010, pp. 432-434, 2010, ACM, 978-1-60558-812-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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19 | Ming-Der Shieh, Tai-Ping Wang, Der-Wei Yang |
Low-power register-exchange survivor memory architectures for Viterbi decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 3(2), pp. 83-90, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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19 | Matthias Kamuf, Viktor Öwall, John B. Anderson |
Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 54-II(6), pp. 537-541, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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19 | Dalia A. El-Dib, Mohamed I. Elmasry |
Modified register-exchange Viterbi decoder for low-power wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2), pp. 371-378, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre |
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 35-44, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wireless LAN, OFDM, viterbi |
17 | Fei Sun, Tong Zhang 0002 |
Parallel high-throughput limited search trellis decoder VLSI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1013-1022, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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17 | Yun-Nan Chang |
Design of soft-output Viterbi decoders with hybrid trace-back processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 69-72, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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9 | Robert Cypher, C. Bernard Shung |
Generalized trace-back techniques for survivor memory management in the Viterbi algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(1), pp. 85-94, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
trace-back, survivor memory, VLSI area requirements, Viterbi algorithm |
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