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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 8 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Sudarshan K. Srinivasan, Miroslav N. Velev |
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. |
MEMOCODE |
2003 |
DBLP DOI BibTeX RDF |
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33 | Matthias Menge |
Superskalare Prozessoren. |
Inform. Spektrum |
1998 |
DBLP DOI BibTeX RDF |
Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer |
33 | B. Ramakrishna Rau |
Dynamically scheduled VLIW processors. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors |
25 | Roland E. Wunderlich, James C. Hoe |
In-system FPGA prototyping of an itanium microarchitecture. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
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25 | Roland E. Wunderlich, James C. Hoe |
In-System FPGA Prototyping of an Itanium Microarchitecture. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
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25 | Peter Marwedel, Birgit Sirocic |
Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing. |
MSE |
2003 |
DBLP DOI BibTeX RDF |
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25 | D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello |
Micronets: a model for decentralising control in asynchronous processor architectures. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency |
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