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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 9 occurrences of 8 keywords
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Results
Found 17 publication records. Showing 17 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | R. S. Hogg, David W. Lloyd, W. I. Hughes |
Self-Timed Communication Strategies for Massively Parallel Systolic Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 557-567, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Scalable, Elastic, Massively-Parallel, Self-timing, Bit-serial |
24 | Ravichandran Ramachandran, Shih-Lien Lu |
Efficient arithmetic using self-timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(4), pp. 445-454, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Hans M. Jacobson, Ganesh Gopalakrishnan |
Asynchronous Microengines for Efficient High-level Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 201-218, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous circuits, microprogramming, self-timing |
12 | Saleh Abdel-Hafeez, Shadi M. Harb |
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 17(3-4), pp. 141-148, May-July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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12 | Krashna Nand Mishra, Yogeshbhai Vallabhbhai Patel |
Creating Fastest Self timing Reference Path for High Speed Memory Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 145-150, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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12 | Roman Fragasse, Ramy Tantawy, Brian Dupaix, Trevor Dean, Daron Disabato, Matthew R. Belz, Dale Shane Smith, Jamin J. McCue, Waleed Khalil |
Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6), pp. 2037-2050, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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12 | Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu 0019, Jun Yang 0006 |
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019, Qingdao, China, July 17-19, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-5520-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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12 | Ivan E. Sutherland |
Self-timing: a step beyond synchrony (tutorial talk). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: International Conference on Formal Methods in Computer-Aided Design, FMCAD '11, Austin, TX, USA, October 30 - November 02, 2011, pp. 2, 2011, FMCAD Inc., 978-0-9835678-1-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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12 | U. Fat Chio, He Gong Wei, Yan Zhu 0001, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins |
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1164-1167, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Kenji Takao, Toru Yamamoto, Takao Hinamoto |
Design of a memory-based self-timing PID controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: 43rd IEEE Conference on Decision and Control, CDC 2004, Nassau, Bahamas, December 14-17, 2004, pp. 1598-1603, 2004, IEEE, 0-7803-8682-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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12 | Eckhard Grass, Richard C. S. Morling, Izzet Kale |
Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan, pp. 143-149, 1996, IEEE Computer Society, 0-8186-7298-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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12 | Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki |
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(11), pp. 1317-1322, November 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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12 | Ted E. Williams, Mark A. Horowitz |
A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991, pp. 210-217, 1991, IEEE, 0-8186-9151-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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12 | Scott B. Guthery |
Self-Timing Programs and the Quantum Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 31(6), pp. 696-702, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
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8 | Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton |
A General Purpose Behavioural Asynchronous Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 125-134, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Behavioural synthesis, asynchronous synthesis, cryptography |
8 | Jean-Philippe Martin, Lorenzo Alvisi, Michael Dahlin |
Small Byzantine Quorum Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2002 International Conference on Dependable Systems and Networks (DSN 2002), 23-26 June 2002, Bethesda, MD, USA, Proceedings, pp. 374-388, 2002, IEEE Computer Society, 0-7695-1597-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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8 | D. J. Kinniment |
An evaluation of asynchronous addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 137-140, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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