Search results for "spidergon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
112	Jirí Jaros, Vaclav Dvorak	Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs.	GECCO	2010	DBLP DOI BibTeX RDF	fat topologies, spidergon, collective communications, wormhole switching, evolutionary design, communication scheduling
98	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	An Analytical Performance Model for the Spidergon NoC.	AINA	2007	DBLP DOI BibTeX RDF
75	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	Communication Modelling of the Spidergon NoC with Virtual Channels.	ICPP	2007	DBLP DOI BibTeX RDF
75	Luciano Bononi, Nicola Concer	Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
53	Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi	Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network.	NOCS	2008	DBLP DOI BibTeX RDF	System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects
45	Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi	An interconnection architecture for network-on-chip systems.	Telecommun. Syst.	2008	DBLP DOI BibTeX RDF	Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects
45	Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi	Quarc: A Novel Network-On-Chip Architecture.	ICPADS	2008	DBLP DOI BibTeX RDF
30	Fadi N. Sibai, Abu Asaduzzaman, Ali El-Moursy	3D layout of the Spidergon-Donut on-chip interconnection network.	Int. J. High Perform. Syst. Archit.	2023	DBLP DOI BibTeX RDF
30	Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas	Improving Reliability in Spidergon Network on Chip-Microprocessors.	MWSCAS	2020	DBLP DOI BibTeX RDF
30	Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi	3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.	ISPAN-FCST-ISCC	2017	DBLP DOI BibTeX RDF
30	Marwah Albughdar, Ausif Mahmood	Maximally Adaptive, Deadlock-Free Routing in Spidergon-Donut Network for Large Multicore NOCs.	ISPDC	2015	DBLP DOI BibTeX RDF
30	Rimpy Bishnoi, Pankaj Kumar Srivastava, Vijay Laxmi, Manoj Singh Gaur, Apoorva Sikka	Distributed adaptive routing for spidergon NoC.	VDAT	2014	DBLP DOI BibTeX RDF
30	Florentine Dubois, José Cano 0001, Marcello Coppola, José Flich, Frédéric Pétrot	Spidergon STNoC design flow.	NOCS	2011	DBLP DOI BibTeX RDF
30	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Partha P. Maji	An analytical performance model for the Spidergon NoC with virtual channels.	J. Syst. Archit.	2010	DBLP DOI BibTeX RDF
30	Marcello Coppola	Spidergon STNoC: The technology that adds value to your System.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
30	Khaldon Hassan, Marcello Coppola	Off-Chip SDRAM Access Through Spidergon STNoC.	ISVLSI (Selected papers)	2010	DBLP DOI BibTeX RDF
30	Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola	Error resilience of intra-die and inter-die communication with 3D spidergon STNoC.	DATE	2010	DBLP DOI BibTeX RDF
30	Mohamed Bakhouya, Suboh A. Suboh, Jaafar Gaber, Tarek A. El-Ghazawi	Analytical performance comparison of 2D Mesh, WK-recursive, and Spidergon NoCs.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
30	Marcello Coppola	3D self testing with Spidergon STNoC.	VTS	2010	DBLP DOI BibTeX RDF
30	Mahmoud Moadeli, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	An Analytical Comparison of the Spidergon and Rectangular Mesh NoCs.	J. Interconnect. Networks	2009	DBLP DOI BibTeX RDF
30	Nicola Concer, Salvatore Iamundo, Luciano Bononi	aEqualized: A novel routing algorithm for the Spidergon Network On Chip.	DATE	2009	DBLP DOI BibTeX RDF
30	Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Alberto Scandurra	Spidergon: a novel on-chip communication network.	SoC	2004	DBLP DOI BibTeX RDF
23	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	Modeling Differentiated Services-Based QoS in Wormhole-Routed NoCs.	AINA	2008	DBLP DOI BibTeX RDF	Perfromance modelling, QoS, Network on Chip, Wormhole
23	Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola	Application-Specific Topology Design Customization for STNoC.	DSD	2007	DBLP DOI BibTeX RDF
23	Luciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli	NoC Topologies Exploration based on Mapping and Simulation Models.	DSD	2007	DBLP DOI BibTeX RDF