Search results for "subtracter"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Albrecht P. Stroele	BIST Pattern Generators Using Addition and Subtraction Operations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, adder, accumulator, pattern generator, subtracter
36	Brett Mathis, James E. Stine	A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter.	ISVLSI	2019	DBLP DOI BibTeX RDF
36	Brett Mathis, James E. Stine	A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter.	ASAP	2019	DBLP DOI BibTeX RDF
36	Karamdeep Singh, Gurmeet Kaur, Maninder Lal Singh	Enhanced performance of all-optical half-subtracter based on cross-gain modulation (XGM) in semiconductor optical amplifier (SOA) by accelerating its gain recovery dynamics.	Photonic Netw. Commun.	2017	DBLP DOI BibTeX RDF
36	Minghui Li, Fangfang Liu, Ming Song, Xiangxiang Chen 0003, Yafei Dong	A Half-Subtracter Calculation Model Based on Stand Displacement Technology.	BIC-TA	2015	DBLP DOI BibTeX RDF
36	Per Karlström, Wenbiao Zhou, Dake Liu	Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study.	EUC	2010	DBLP DOI BibTeX RDF
36	Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma	Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
36	Gururaj S. Rao, A. V. Krishnamurthy, M. Nagesh Rao	A negative-binary adder-subtracter.	IEEE Symposium on Computer Arithmetic	1972	DBLP DOI BibTeX RDF
22	K. C. Ho 0001, Xiaoning Lu, Vandana Mehta	Adaptive Blind Narrowband Interference Cancellation for Multi-User Detection.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
22	Yuan Zhang, Youren Wang, Shanshan Yang, Min Xie	Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance.	ICES	2007	DBLP DOI BibTeX RDF	Embryonic systems, Two-level self-repair, Extended hamming code, Fault tolerance of configuration memory, Cellular arrays
22	Cecília Reis, José António Tenreiro Machado, José Boaventura Cunha, Eduardo José Solteiro Pires	Evolutionary computation in the design of logic circuits.	SMC	2007	DBLP DOI BibTeX RDF
22	Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh	A low-power high-SFDR CMOS direct digital frequency synthesizer.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
22	Jesus Garcia, Mark G. Arnold, Leonidas G. Bleris, Mayuresh V. Kothare	LNS architectures for embedded model predictive control processors.	CASES	2004	DBLP DOI BibTeX RDF	FWL, cotransformation, reduced precision, LNS, MPC
22	Jaeyoung Kwak, Sang-Sic Yoon, Hung-Jun Kwon, Kwyro Lee	A design of the new FPGA with data path logic and run time block reconfiguration method.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
22	Gwangwoo Choe, Earl E. Swartzlander Jr.	Bipolar merged arithmetic for wavelet architectures.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
22	Lim Chu Aun, S. M. Rezaul Hasan	An all Digital BiCMOS Phase Lock Loop for VLSI Processors.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
22	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	The Half-Adder Form and Early Branch Condition Resolution.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction
22	Yamin Li, Wanming Chu	Implementation of single precision floating point square root on FPGAs.	FCCM	1997	DBLP DOI BibTeX RDF
22	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	Early Zero Detection.	ICCD	1996	DBLP DOI BibTeX RDF	half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP
22	Miriam Leeser, John W. O'Leary	Verification of a subtractive radix-2 square root algorithm and implementation.	ICCD	1995	DBLP DOI BibTeX RDF	subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations