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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 16 keywords
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Results
Found 20 publication records. Showing 20 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Albrecht P. Stroele |
BIST Pattern Generators Using Addition and Subtraction Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 69-80, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
built-in self-test, adder, accumulator, pattern generator, subtracter |
36 | Brett Mathis, James E. Stine |
A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pp. 278-283, 2019, IEEE, 978-1-7281-3391-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Brett Mathis, James E. Stine |
A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019, pp. 227-234, 2019, IEEE, 978-1-7281-1601-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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36 | Karamdeep Singh, Gurmeet Kaur, Maninder Lal Singh |
Enhanced performance of all-optical half-subtracter based on cross-gain modulation (XGM) in semiconductor optical amplifier (SOA) by accelerating its gain recovery dynamics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 34(1), pp. 111-130, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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36 | Minghui Li, Fangfang Liu, Ming Song, Xiangxiang Chen 0003, Yafei Dong |
A Half-Subtracter Calculation Model Based on Stand Displacement Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIC-TA ![In: Bio-Inspired Computing - Theories and Applications - 10th International Conference, BIC-TA 2015, Hefei, China, September 25-28, 2015, Proceedings, pp. 225-231, 2015, Springer, 978-3-662-49013-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Per Karlström, Wenbiao Zhou, Dake Liu |
Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, EUC 2010, Hong Kong, China, 11-13 December 2010, pp. 68-72, 2010, IEEE Computer Society, 978-0-7695-4322-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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36 | Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma |
Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(6), pp. 1437-1444, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
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36 | Gururaj S. Rao, A. V. Krishnamurthy, M. Nagesh Rao |
A negative-binary adder-subtracter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 2nd IEEE Symposium on Computer Arithmetic, ARITH 1972, College Park, MD, USA, May 15-16, 1972, pp. 1-9, 1972, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1972 |
DBLP DOI BibTeX RDF |
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22 | K. C. Ho 0001, Xiaoning Lu, Vandana Mehta |
Adaptive Blind Narrowband Interference Cancellation for Multi-User Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(3), pp. 1024-1033, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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22 | Yuan Zhang, Youren Wang, Shanshan Yang, Min Xie |
Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 129-139, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Embryonic systems, Two-level self-repair, Extended hamming code, Fault tolerance of configuration memory, Cellular arrays |
22 | Cecília Reis, José António Tenreiro Machado, José Boaventura Cunha, Eduardo José Solteiro Pires |
Evolutionary computation in the design of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Montréal, Canada, 7-10 October 2007, pp. 1664-1669, 2007, IEEE, 978-1-4244-0990-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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22 | Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh |
A low-power high-SFDR CMOS direct digital frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1670-1673, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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22 | Jesus Garcia, Mark G. Arnold, Leonidas G. Bleris, Mayuresh V. Kothare |
LNS architectures for embedded model predictive control processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 79-84, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FWL, cotransformation, reduced precision, LNS, MPC |
22 | Jaeyoung Kwak, Sang-Sic Yoon, Hung-Jun Kwon, Kwyro Lee |
A design of the new FPGA with data path logic and run time block reconfiguration method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 467-469, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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22 | Gwangwoo Choe, Earl E. Swartzlander Jr. |
Bipolar merged arithmetic for wavelet architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 462-465, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Lim Chu Aun, S. M. Rezaul Hasan |
An all Digital BiCMOS Phase Lock Loop for VLSI Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 318-320, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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22 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
The Half-Adder Form and Early Branch Condition Resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 266-273, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction |
22 | Yamin Li, Wanming Chu |
Implementation of single precision floating point square root on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 226-233, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
Early Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 545-, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP |
22 | Miriam Leeser, John W. O'Leary |
Verification of a subtractive radix-2 square root algorithm and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 526-531, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations |
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