Search results for "subtracters"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57	Albrecht P. Stroele	Test response compaction using arithmetic functions.	VTS	1996	DBLP DOI BibTeX RDF	arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units
42	Nikos Temenos, Paul P. Sotiriadis	Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
42	Ankita Nandi, Chandan Kumar Jha 0001, Joycee Mekie	Tunable Inexact Subtracters for Division in Image Processing Applications.	MWSCAS	2020	DBLP DOI BibTeX RDF
42	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.	ICESS	2007	DBLP DOI BibTeX RDF
42	Oscar Gustafsson, Kenny Johansson, Håkan Johansson, Lars Wanhammar	Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Trevor W. Fox, Laurence E. Turner	The design of peak constrained least squares FIR filters with low complexity finite precision coefficients.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
42	Albrecht P. Stroele	BIST Pattern Generators Using Addition and Subtraction Operations.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	built-in self-test, adder, accumulator, pattern generator, subtracter
21	Oscar Gustafsson	A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems.	ISCAS	2007	DBLP DOI BibTeX RDF
21	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	Low power and high-speed implementation of fir filters for software defined radio receivers.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
21	Håkan Johansson, Oscar Gustafsson, J. Johansson, Lars Wanhammar	Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata	A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.	KES	2003	DBLP DOI BibTeX RDF
21	Mitsuru Yamada, Akinori Nishihara	A high-speed FIR digital filter with CSD coefficients implemented on FPGA.	ASP-DAC	2001	DBLP DOI BibTeX RDF
21	Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos	On Accumulator-Based Bit-Serial Test Response Compaction Schemes.	ISQED	2001	DBLP DOI BibTeX RDF
21	Albrecht P. Stroele	Synthesis for Arithmetic Built-In Self-Tes.	VTS	2000	DBLP DOI BibTeX RDF	test configuration, built-in self-test, high-level synthesis, synthesis for testability, Accumulator
21	Yamin Li, Wanming Chu	Implementation of single precision floating point square root on FPGAs.	FCCM	1997	DBLP DOI BibTeX RDF
21	Albrecht P. Stroele	Arithmetic Pattern Generators for Built-In Self-Test.	ICCD	1996	DBLP DOI BibTeX RDF	Arithmetic functions, built-in self-test, design for testability, pattern generator
21	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion