Search results for "super-scalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
41	John Alexander McDermid	Complexity: Concept, Causes and Control.	ICECCS	2000	DBLP DOI BibTeX RDF	internal sources, modern hardware, super-scalar processors, external sources, complexity management, strict dependability requirements, software engineering, embedded systems, risk, product families, computer based systems
41	Minjoong Rim, Rajiv Jain	Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling
29	Masaharu Goto, Toshinori Sato	Leakage Energy Reduction in Register Renaming.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy
25	Kieran T. Herley, David F. Snelling	Architectures and Networks.	Euro-Par	1998	DBLP DOI BibTeX RDF
19	Masatoshi Shima 0001	The Birth, Evolution and Future of the Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
19	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada	A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.	ICCD	1999	DBLP DOI BibTeX RDF	scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch
19	Akihito Takahashi, Stanislav Sedukhin	Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor.	HPCC	2005	DBLP DOI BibTeX RDF
18	Mikhail Asiatici, Damian Maiorano, Paolo Ienne	FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort.	ASAP	2020	DBLP DOI BibTeX RDF
18	Felix Mühlbauer, Lukas Schröder, Mario Schölzel	Handling of transient and permanent faults in dynamically scheduled super-scalar processors.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
18	Mikhail Asiatici, Damian Maiorano, Paolo Ienne	FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
18	Michael Axtmann, Sascha Witt, Daniel Ferizovic, Peter Sanders 0001	In-place Parallel Super Scalar Samplesort (IPSSSSo).	CoRR	2017	DBLP BibTeX RDF
18	Michael Axtmann, Sascha Witt, Daniel Ferizovic, Peter Sanders 0001	In-Place Parallel Super Scalar Samplesort (IPSSSSo).	ESA	2017	DBLP DOI BibTeX RDF
18	Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie	Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.	DSD	2010	DBLP DOI BibTeX RDF
18	Marcin Zukowski, Sándor Héman, Niels Nes, Peter A. Boncz	Super-Scalar RAM-CPU Cache Compression.	ICDE	2006	DBLP DOI BibTeX RDF
18	Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya	Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Peter Sanders 0001, Sebastian Winkel	Super Scalar Sample Sort.	ESA	2004	DBLP DOI BibTeX RDF
18	Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey	Error detection by duplicated instructions in super-scalar processors.	IEEE Trans. Reliab.	2002	DBLP DOI BibTeX RDF
18	Jack Y. B. Lee, C. H. Lee	Design, performance analysis, and implementation of a super-scalar video-on-demand system.	IEEE Trans. Circuits Syst. Video Technol.	2002	DBLP DOI BibTeX RDF
18	Hassan Aljifri, Alexander Perez-Pons, Moiez A. Tapia	The Estimation of the WCET in Super-Scalar Real-Time System.	Scalable Comput. Pract. Exp.	2001	DBLP BibTeX RDF
18	Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno	Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.	ASYNC	2001	DBLP DOI BibTeX RDF
18	Chris Edmondson-Yurkanan	Why you should build a super-scalar pipeline simulator.	WCAE@HPCA	1997	DBLP DOI BibTeX RDF
18	Ramesh C. Agarwal	A Super Scalar Sort Algorithm for RISC Processors.	SIGMOD Conference	1996	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li	Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.	ITC	1996	DBLP DOI BibTeX RDF
18	Babu Turumella, Aiman Kabakibo, Manjunath Bogadi, Karakunakara Menon, Shaleah Thusoo, Long Nguyen, Nirmal R. Saxena, Michael Chow	Design Verification of a Super-Scalar RISC Processor.	FTCS	1995	DBLP DOI BibTeX RDF
18	William F. Appelbe, Srinivas Doddapaneni, Reid Harmon, Phil May, D. Scott Wills, Maurizio Vitale	Hoisting Branch Conditions - Improving Super-Scalar Processor Performance.	LCPC	1995	DBLP DOI BibTeX RDF
18	Pradip Bose	Architectural Timing Verification and Test for Super Scalar Processors.	FTCS	1994	DBLP DOI BibTeX RDF
18	Marc Pouzet	Fine Grain Parallelisation of Functional Programs for VLIW or Super-scalar Architectures.	Applications in Parallel and Distributed Computing	1994	DBLP BibTeX RDF
18	Terence M. Potter, Hsiao-chen Chung, Chuan-lin Wu	Reconfigurable Branch Processing Strategy in Super-Scalar Microprocessors.	ICPP (1)	1993	DBLP DOI BibTeX RDF
18	Edil S. T. Fernandes, Claudson F. Bornstein, Cláudia M. D. Pereira	Parallel code generation for super-scalar architectures.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
18	Edil S. T. Fernandes, Fernando M. B. Barbosa	Effects of Building Blocks on the Performance of Super-Scalar Architectures.	ISCA	1992	DBLP DOI BibTeX RDF
18	Pradip Bose	Early Performance Estimation of Super Scalar Machine Models.	ICCD	1991	DBLP DOI BibTeX RDF
18	Pradip Bose	Optimal Code Generation for Expressions on Super Scalar Machines.	FJCC	1986	DBLP BibTeX RDF
13	Alexandre Duchateau, Albert Sidelnik, María Jesús Garzarán, David A. Padua	P-Ray: A Software Suite for Multi-core Architecture Characterization.	LCPC	2008	DBLP DOI BibTeX RDF
13	Sung-Boem Park, Subhasish Mitra	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.	DAC	2008	DBLP DOI BibTeX RDF	verification, debug, validation, design for debug
13	Youssef N. Naguib, Rafik S. Guindi	Speeding up SystemC simulation through process splitting.	DATE	2007	DBLP DOI BibTeX RDF
13	Marcin Zukowski, Sándor Héman, Peter A. Boncz	Architecture-conscious hashing.	DaMoN	2006	DBLP DOI BibTeX RDF
13	Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie 0001, Narayanan Vijaykrishnan, Rong Luo	Leakage Optimized DECAP Design for FPGAs.	APCCAS	2006	DBLP DOI BibTeX RDF
13	Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe	TurboSMARTS: accurate microarchitecture simulation sampling in minutes.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	checkpointed microarchitecture simulation, simulation sampling
13	Inki Hong, Miodrag Potkonjak, Ramesh Karri	A heterogeneous built-in self-repair approach using system-level synthesis flexibility.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
13	Kentaro Hamayasu, Vasily G. Moshnyaga	Impact of Register-Cache Bandwidth Variation on Processor Performance.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
13	Joshua L. Kihm, Daniel A. Connors	Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling.	ICCD	2004	DBLP DOI BibTeX RDF
13	Aneesh Aggarwal, Manoj Franklin	Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency.	IEEE PACT	2003	DBLP DOI BibTeX RDF	Instruction Replication, Inter-PE communication, Instruction Distribution, Instructions per Cycle, Load Imbalance, Clustered processors
13	Julien Bohbot, Marc Zolver, Diego Klahr, Arnaud Torres	Three Dimensional Modelling of Combustion in a Direct Injection Diesel Engine Using a New Unstructured Parallel Solver.	ICCSA (1)	2003	DBLP DOI BibTeX RDF
13	P. H. Chan, Jack Y. B. Lee	An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System.	ASAP	2003	DBLP DOI BibTeX RDF
13	Rafael R. dos Santos, Tatiana Gadelha Serra dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky	Complex Branch Profiling for Dynamic Conditional Execution.	SBAC-PAD	2003	DBLP DOI BibTeX RDF
13	Soner Önder	Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets.	IEEE PACT	2002	DBLP DOI BibTeX RDF	load speculation, memory dependence prediction, store sets, wide issue superscalar, speculative execution
13	Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven	A 2D Addressing Mode for Multimedia Applications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
13	Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero	Fetching instruction streams.	MICRO	2002	DBLP DOI BibTeX RDF	Systems Application Architecture
13	Mahmut T. Kandemir, J. Ramanujam	Data Relation Vectors: A New Abstraction for Data Optimizations.	IEEE PACT	2000	DBLP DOI BibTeX RDF
13	André Hergenhan, Wolfgang Rosenstiel	Static Timing Analysis of Embedded Software on Advanced Processor Architectures.	DATE	2000	DBLP DOI BibTeX RDF
13	Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad	Characterizing processor architectures for programmable network interfaces.	ICS	2000	DBLP DOI BibTeX RDF
13	Ramesh V. Peri, Srinivas Doddapaneni	Compilers and Tools for Embedded Systems - Introduction.	HICSS	2000	DBLP DOI BibTeX RDF
13	Derek L. Howard, Mikko H. Lipasti	The Effect of Program Optimization on Trace Cache Efficiency.	IEEE PACT	1999	DBLP DOI BibTeX RDF	compiler optimization, Microarchitecture, superscalar processors, trace cache
13	B. Grayson, L. John, C. Chase	The effects of memory-access ordering on multiple-issue uniprocessor performance.	IPCCC	1999	DBLP DOI BibTeX RDF
13	Miroslav N. Velev, Randal E. Bryant	Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic.	CHARME	1999	DBLP DOI BibTeX RDF
13	Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham	Improving Witness Search Using Orders on States.	ICCD	1999	DBLP DOI BibTeX RDF
13	John L. Ross, Shmuel Sagiv	Building a Bridge between Pointer Aliases and Program Dependences.	ESOP	1998	DBLP DOI BibTeX RDF
13	Omar Hammami	Performance Impacts of Superscalar Microarchitecture on SOM Execution.	Annual Simulation Symposium	1998	DBLP DOI BibTeX RDF
13	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
13	Corinna G. Lee, Derek J. DeVries	Initial Results on the Performance and Cost of Vector Microprocessors.	MICRO	1997	DBLP DOI BibTeX RDF
13	Jeremy D. Frens, David S. Wise	Auto-blocking Matrix-Multiplication or Tracking BLAS3 Performance with Source Code.	PPoPP	1997	DBLP DOI BibTeX RDF	indexing, storage management, paging, quadtrees, cache misses, swapping
13	Waleed Meleis, Edward S. Davidson	Optimal local register allocation for a multiple-issue machine.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF