Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
41 | John Alexander McDermid |
Complexity: Concept, Causes and Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 6th International Conference on Engineering of Complex Computer Systems (ICECCS 2000), 11-15 September 2000, Tokyo, Japan, pp. 2-, 2000, IEEE Computer Society, 0-7695-0583-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
internal sources, modern hardware, super-scalar processors, external sources, complexity management, strict dependability requirements, software engineering, embedded systems, risk, product families, computer based systems |
41 | Minjoong Rim, Rajiv Jain |
Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(4), pp. 399-410, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling |
29 | Masaharu Goto, Toshinori Sato |
Leakage Energy Reduction in Register Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 23-24 March 2004, Hachioji, Tokyo, Japan, pp. 890-895, 2004, IEEE Computer Society, 0-7695-2087-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy |
25 | Kieran T. Herley, David F. Snelling |
Architectures and Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '98 Parallel Processing, 4th International Euro-Par Conference, Southampton, UK, September 1-4, 1998, Proceedings, pp. 967-969, 1998, Springer, 3-540-64952-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Masatoshi Shima 0001 |
The Birth, Evolution and Future of the Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China, pp. 2, 2005, IEEE Computer Society, 0-7695-2432-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada |
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 279-280, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch |
19 | Akihito Takahashi, Stanislav Sedukhin |
Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, First International Conference, HPCC 2005, Sorrento, Italy, September 21-23, 2005, Proceedings, pp. 786-795, 2005, Springer, 3-540-29031-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Mikhail Asiatici, Damian Maiorano, Paolo Ienne |
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 31st IEEE International Conference on Application-specific Systems, Architectures and Processors , ASAP 2020, Manchester, United Kingdom, July 6-8, 2020, pp. 133-140, 2020, IEEE, 978-1-7281-7147-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Felix Mühlbauer, Lukas Schröder, Mario Schölzel |
Handling of transient and permanent faults in dynamically scheduled super-scalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 80, pp. 176-183, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Mikhail Asiatici, Damian Maiorano, Paolo Ienne |
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018, pp. 294, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Michael Axtmann, Sascha Witt, Daniel Ferizovic, Peter Sanders 0001 |
In-place Parallel Super Scalar Samplesort (IPSSSSo). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1705.02257, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
18 | Michael Axtmann, Sascha Witt, Daniel Ferizovic, Peter Sanders 0001 |
In-Place Parallel Super Scalar Samplesort (IPSSSSo). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: 25th Annual European Symposium on Algorithms, ESA 2017, September 4-6, 2017, Vienna, Austria, pp. 9:1-9:14, 2017, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-049-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie |
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France, pp. 269-272, 2010, IEEE Computer Society, 978-0-7695-4171-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Marcin Zukowski, Sándor Héman, Niels Nes, Peter A. Boncz |
Super-Scalar RAM-CPU Cache Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the 22nd International Conference on Data Engineering, ICDE 2006, 3-8 April 2006, Atlanta, GA, USA, pp. 59, 2006, IEEE Computer Society, 0-7695-2570-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya |
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 373-379, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Peter Sanders 0001, Sebastian Winkel |
Super Scalar Sample Sort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA 2004, 12th Annual European Symposium, Bergen, Norway, September 14-17, 2004, Proceedings, pp. 784-796, 2004, Springer, 3-540-23025-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey |
Error detection by duplicated instructions in super-scalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 51(1), pp. 63-75, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Jack Y. B. Lee, C. H. Lee |
Design, performance analysis, and implementation of a super-scalar video-on-demand system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 12(11), pp. 983-997, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hassan Aljifri, Alexander Perez-Pons, Moiez A. Tapia |
The Estimation of the WCET in Super-Scalar Real-Time System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scalable Comput. Pract. Exp. ![In: Scalable Comput. Pract. Exp. 4(2), 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
18 | Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno |
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 162-172, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Chris Edmondson-Yurkanan |
Why you should build a super-scalar pipeline simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1997 workshop on Computer architecture education, WCAE@HPCA 1997, San Antonio, Texas, USA, February 1997, pp. 3, 1997, ACM, 978-1-4503-4739-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Ramesh C. Agarwal |
A Super Scalar Sort Algorithm for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 1996 ACM SIGMOD International Conference on Management of Data, Montreal, Quebec, Canada, June 4-6, 1996., pp. 240-246, 1996, ACM Press, 978-0-89791-794-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li |
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 904-913, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Babu Turumella, Aiman Kabakibo, Manjunath Bogadi, Karakunakara Menon, Shaleah Thusoo, Long Nguyen, Nirmal R. Saxena, Michael Chow |
Design Verification of a Super-Scalar RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-25, The Twenty-Fifth International Symposium on Fault-Tolerant Computing, Pasadena, California, USA, June 27-30, 1995, pp. 472-477, 1995, IEEE Computer Society, 0-8186-7079-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | William F. Appelbe, Srinivas Doddapaneni, Reid Harmon, Phil May, D. Scott Wills, Maurizio Vitale |
Hoisting Branch Conditions - Improving Super-Scalar Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 8th International Workshop, LCPC'95, Columbus, Ohio, USA, August 10-12, 1995, Proceedings, pp. 304-317, 1995, Springer, 3-540-60765-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Pradip Bose |
Architectural Timing Verification and Test for Super Scalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS/24, The Twenty-Fourth Annual International Symposium on Fault-Tolerant Computing, Austin, Texas, USA, June 15-17, 1994, pp. 256-265, 1994, IEEE Computer Society, 0-8186-5520-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
18 | Marc Pouzet |
Fine Grain Parallelisation of Functional Programs for VLIW or Super-scalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Applications in Parallel and Distributed Computing ![In: Applications in Parallel and Distributed Computing, Proceedings of the IFIP WG10.3 Working Conference on Applications in Parallel and Distributed Computing, Caracas, Venezuela, 18-22 April, 1994, pp. 195-204, 1994, North-Holland, 0-444-81870-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
18 | Terence M. Potter, Hsiao-chen Chung, Chuan-lin Wu |
Reconfigurable Branch Processing Strategy in Super-Scalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume I: Architecture., pp. 47-50, 1993, CRC Press, 0-8493-8984-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
18 | Edil S. T. Fernandes, Claudson F. Bornstein, Cláudia M. D. Pereira |
Parallel code generation for super-scalar architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 34(1-5), pp. 223-226, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Edil S. T. Fernandes, Fernando M. B. Barbosa |
Effects of Building Blocks on the Performance of Super-Scalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 36-45, 1992, ACM, 0-89791-509-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Pradip Bose |
Early Performance Estimation of Super Scalar Machine Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 388-392, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
18 | Pradip Bose |
Optimal Code Generation for Expressions on Super Scalar Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FJCC ![In: Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, pp. 372-379, 1986, IEEE Computer Society, 0-8186-0743-2. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
13 | Alexandre Duchateau, Albert Sidelnik, María Jesús Garzarán, David A. Padua |
P-Ray: A Software Suite for Multi-core Architecture Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 21th International Workshop, LCPC 2008, Edmonton, Canada, July 31 - August 2, 2008, Revised Selected Papers, pp. 187-201, 2008, Springer, 978-3-540-89739-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Sung-Boem Park, Subhasish Mitra |
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 373-378, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
verification, debug, validation, design for debug |
13 | Youssef N. Naguib, Rafik S. Guindi |
Speeding up SystemC simulation through process splitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 111-116, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
13 | Marcin Zukowski, Sándor Héman, Peter A. Boncz |
Architecture-conscious hashing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DaMoN ![In: Workshop on Data Management on New Hardware, DaMoN 2006, Chicago, Illinois, USA, June 25, 2006, pp. 6, 2006, ACM, 1-59593-466-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie 0001, Narayanan Vijaykrishnan, Rong Luo |
Leakage Optimized DECAP Design for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 960-963, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe |
TurboSMARTS: accurate microarchitecture simulation sampling in minutes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2005, June 6-10, 2005, Banff, Alberta, Canada, pp. 408-409, 2005, ACM, 1-59593-022-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
checkpointed microarchitecture simulation, simulation sampling |
13 | Inki Hong, Miodrag Potkonjak, Ramesh Karri |
A heterogeneous built-in self-repair approach using system-level synthesis flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(1), pp. 93-101, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Kentaro Hamayasu, Vasily G. Moshnyaga |
Impact of Register-Cache Bandwidth Variation on Processor Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 212-225, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Joshua L. Kihm, Daniel A. Connors |
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 326-331, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Aneesh Aggarwal, Manoj Franklin |
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 46-55, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Instruction Replication, Inter-PE communication, Instruction Distribution, Instructions per Cycle, Load Imbalance, Clustered processors |
13 | Julien Bohbot, Marc Zolver, Diego Klahr, Arnaud Torres |
Three Dimensional Modelling of Combustion in a Direct Injection Diesel Engine Using a New Unstructured Parallel Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2003, International Conference, Montreal, Canada, May 18-21, 2003, Proceedings, Part I, pp. 483-492, 2003, Springer, 3-540-40155-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | P. H. Chan, Jack Y. B. Lee |
An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 271-281, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Rafael R. dos Santos, Tatiana Gadelha Serra dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky |
Complex Branch Profiling for Dynamic Conditional Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 10-12 November 2003, Sao Paulo, Brazil, pp. 28-35, 2003, IEEE Computer Society, 0-7695-2046-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Soner Önder |
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 232-241, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
load speculation, memory dependence prediction, store sets, wide issue superscalar, speculative execution |
13 | Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven |
A 2D Addressing Mode for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Processor Design Challenges ![In: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, pp. 291-306, 2002, Springer, 3-540-43322-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero |
Fetching instruction streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 371-382, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Systems Application Architecture |
13 | Mahmut T. Kandemir, J. Ramanujam |
Data Relation Vectors: A New Abstraction for Data Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 227-236, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | André Hergenhan, Wolfgang Rosenstiel |
Static Timing Analysis of Embedded Software on Advanced Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 552-559, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad |
Characterizing processor architectures for programmable network interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 54-65, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Ramesh V. Peri, Srinivas Doddapaneni |
Compilers and Tools for Embedded Systems - Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA, 2000, IEEE Computer Society, 0-7695-0493-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Derek L. Howard, Mikko H. Lipasti |
The Effect of Program Optimization on Trace Cache Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 256-261, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
compiler optimization, Microarchitecture, superscalar processors, trace cache |
13 | B. Grayson, L. John, C. Chase |
The effects of memory-access ordering on multiple-issue uniprocessor performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 293-302, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Miroslav N. Velev, Randal E. Bryant |
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 37-53, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham |
Improving Witness Search Using Orders on States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 452-457, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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13 | John L. Ross, Shmuel Sagiv |
Building a Bridge between Pointer Aliases and Program Dependences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESOP ![In: Programming Languages and Systems - ESOP'98, 7th European Symposium on Programming, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 221-235, 1998, Springer, 3-540-64302-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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13 | Omar Hammami |
Performance Impacts of Superscalar Microarchitecture on SOM Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 31st Annual Simulation Symposium (SS '98), 5-9 April 1998, Boston, MA, USA, pp. 202-209, 1998, IEEE Computer Society, 0-8186-8418-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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13 | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen |
Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 15(3), pp. 322-354, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference |
13 | Corinna G. Lee, Derek J. DeVries |
Initial Results on the Performance and Cost of Vector Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 171-182, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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13 | Jeremy D. Frens, David S. Wise |
Auto-blocking Matrix-Multiplication or Tracking BLAS3 Performance with Source Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), Las Vegas, Nevada, USA, June 18-21, 1997, pp. 206-216, 1997, ACM, 0-89791-906-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
indexing, storage management, paging, quadtrees, cache misses, swapping |
13 | Waleed Meleis, Edward S. Davidson |
Optimal local register allocation for a multiple-issue machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 107-116, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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