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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li |
Fine-grained write scheduling for PCM performance improvement under write power budget. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015, pp. 19-24, 2015, IEEE, 978-1-4673-8009-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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19 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 72-82, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
16 | Bowen Huang, Jianwei Liao 0001, Jun Li 0062, Yang Chen, Zhigang Cai, Yuanquan Shi |
Read disturb-aware write scheduling and data reallocation in SSDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 17(8), pp. 20200015, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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16 | Jun Li 0062, Xiaofei Xu, Xiaoning Peng, Jianwei Liao 0001 |
Pattern-based Write Scheduling and Read Balance-oriented Wear-Leveling for Solid State Drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSST ![In: 35th Symposium on Mass Storage Systems and Technologies, MSST 2019, Santa Clara, CA, USA, May 20-24, 2019, pp. 126-133, 2019, IEEE, 978-1-7281-3920-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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16 | Ying Wang 0001, Yinhe Han 0001, Huawei Li 0001, Lei Zhang 0008, Yuanqing Cheng, Xiaowei Li 0001 |
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(5), pp. 1613-1625, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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12 | Chitra Natarajan, Bruce Christenson, Faye A. Briggs |
A study of performance impact of memory controller features in multi-processor server environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 80-87, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact |
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