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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Lars Luchterhandt, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Mueller, Babak Sadiye |
Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-7, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | Iwan Feras Fattohi, Christian Prehofer, Frank Slomka |
Worst-Case Response Time Analysis of Earliest Deadline First in an Industrial Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-8, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | |
Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023 ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![VDE/IEEE, 978-3-8007-6065-7 The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | Julius Roob, Anoop Bhagyanath, Klaus Schneider 0001 |
Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-12, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | Philipp Schmitz, Johannes Mueller, Christian Bartsch 0001, Dominik Stoffel, Wolfgang Kunz |
UPEC-PN: Exhaustive constant time verification of low-level software using property checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-8, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich |
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-12, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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1 | Johannes Schreiner, Vasundhara Raje Gontia, Sebastian Prebeck, Wolfgang Ecker |
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2023, 26th Workshop, Freiburg, Germany, 23-24 March 2023, pp. 1-12, 2023, VDE/IEEE, 978-3-8007-6065-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
1 | Omair Rafique, Klaus Schneider 0001 |
Data-aware Global Scheduling of Dataflow Process Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-9, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Alireza Mahzoon, Rolf Drechsler |
Polynomial Formal Verification of Complex Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-4, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Klaus Schneider 0001, Anoop Bhagyanath, Julius Roob |
Virtual Buffers for Exposed Datapath Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-11, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Lukas Mentel, Karsten Scheibler, Tino Teige |
Detection and Elimination of Constants to Strengthen k-Induction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-10, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Ming Hu, Leonore Winterer, Ralf Wimmer 0001 |
Diagnosing Partially Observable Markov Decision Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-10, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Tobias Seufert, Christoph Scholl 0001, Arun Chandrasekharan, Sven Reimer, Tobias Welp |
Making PROGRESS in Property Directed Reachability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-2, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | |
Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022 ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![VDE/IEEE, 978-3-8007-5754-1 The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker |
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-9, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Christian Bartsch 0001, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz |
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-4, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Mehran Goli, Rolf Drechsler |
Simulation-based Verification of SystemC-based VPs at the ESL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2022, 25th Workshop, Virtual Event, Germany, February 17-18, 2022, pp. 1-4, 2022, VDE/IEEE, 978-3-8007-5754-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
1 | Lukas Steiner, Matthias Jung 0001, Norbert Wehn |
Exploration of DDR5 with the Open-Source Simulator DRAMSys. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-11, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Jie Hou, Martin Radetzki |
Comprehensive modeling and evaluation of Network-on-Chip performability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-12, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker |
On Self-Verifying DSL Generation for Embedded Systems Automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-7, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Felix Winterer, Tobias Seufert, Karsten Scheibler, Tino Teige, Chritsoph Scholl, Bernd Becker 0001 |
ICP and IC3 with Stronger Generalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-12, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Lukas Mentel, Karsten Scheibler, Felix Winterer, Bernd Becker 0001, Tino Teige |
Benchmarking SMT Solvers on Automotive Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-10, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt |
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-8, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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1 | |
Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021 ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![VDE/IEEE, 978-3-8007-5500-4 The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker |
Extending Verilator to Enable Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-6, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Martín Letras, Joachim Falk, Jürgen Teich |
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-11, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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1 | Christoph Grimm 0001, Frank Wawrzik, Alexander Louis-Ferdinand Jung, Konstantin Lübeck, Sebastian Post, Johannes Koch, Oliver Bringmann 0001 |
APPEL - AGILA ProPErty and Dependency Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-11, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
1 | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-8, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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1 | Max Brand, Albrecht Mayer, Frank Slomka |
A Matter of Overhead - Response Time Analysis of Hard Real-Time Systems in Theory and Practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2021, 24th Workshop, Virtual Event, Germany, March 18-19, 2021, pp. 1-7, 2021, VDE/IEEE, 978-3-8007-5500-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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1 | Jens Rudolf, Florian Grützmacher, Christian Haubelt |
Model-based Analysis of Sensor-Subsystems Using Scenario-Aware Dataflow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-9, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
1 | Daniel Luenemann, Maher Fakih, Kim Grüttner |
Capturing Neural-Networks as Synchronous Dataflow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-10, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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1 | Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt |
A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-8, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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1 | Jakob Heller, Christoph Niemann 0002, Franz Plocksties, Christian Haubelt, Dirk Timmermann |
Towards Virtual Prototyping of Electrically Active Implants Using SystemC-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-8, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
1 | Martin Köhler, Felix Hasselwander, Klaus Schneider 0001 |
Properties of Invariants and Induction Lemmata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-10, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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1 | |
23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020 ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![VDE / IEEE, 978-3-8007-5220-1 The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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1 | Jens Froemmer, Yara Gowayed, Nico Bannow, Wolfgang Kunz, Christoph Grimm 0001, Klaus Schneider 0001 |
Area Estimation Framework for Digital Hardware Design using Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 23rd GMM/ITG/GI Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2020, Stuttgart, Germany, March 19-20, 2020, pp. 1-10, 2020, VDE / IEEE, 978-3-8007-5220-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
1 | Görschwin Fey, Rolf Drechsler |
Self-Explaining Digital Systems - Some Technical Steps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-8, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | |
22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![VDE Verlag, 978-3-8007-4945-4 The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Jens Rudolf, Manuel Strobel, Joscha Benz, Christian Haubelt, Martin Radetzki, Oliver Bringmann 0001 |
Automated Sensor Firmware Development - Generation, Optimization, and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-12, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken |
Logic Optimization of Majority-Inverter Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-4, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Michael Schwarz 0010, Dominik Stoffel, Wolfgang Kunz |
ACCESS: HW/SW-Co-Equivalence Checking for Firmware Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-4, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz |
How to Keep 4-Eyes Principle in a Design and Property Generation Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-6, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Martin Köhler, Klaus Schneider 0001 |
Inductive Proof Rules Beyond Safety Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-9, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Markus Hedderich, Markus Heimberger, Axel Klekamp |
SEMAS - System Engineering Methodology for Automated Systems | The world described in layers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-9, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Iryna Kmitina, Nico Bannow, Christoph Grimm 0001, Daniel Zielinski, Carna Zivkovic |
Optimization Framework for Hardware Design of Engine Control Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-8, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Fin Hendrik Bahnsen, Görschwin Fey |
Approximation of Neural Networks for Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, MBMV 2019, Kaiserslautern, Germany, March 8-9, 2019., pp. 1-10, 2019, VDE Verlag, 978-3-8007-4945-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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1 | Marcel Rieß, Cedrik Bock, Frank Slomka |
Generic Reusable Hardware/Software Co-Design Implementation of a Complete FH-FSK Modem for Robust Multi-User Acoustic Underwater Communication and System Validation on a FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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1 | Johannes Mast, Stefan Rädle, Joachim Gerlach |
Modellbasierte Analyse und Multikriterien-Optimierung komplexer Systemszenarien unter Anwendung von Methoden der Künstlichen Intelligenz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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1 | Ralf Wimmer 0001, Andreas Karrenbauer, Ruben Becker, Christoph Scholl 0001, Bernd Becker 0001 |
From DQBF to QBF by Dependency Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf |
ScaLP: A Light-Weighted (MI)LP-Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Kai Neubauer, Christian Haubelt, Philipp Wanko, Torsten Schaub |
Systematic Test Case Instance Generation for the Assessment of System-level Design Space Exploration Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Leonore Winterer, Sebastian Junges, Ralf Wimmer 0001, Nils Jansen 0001, Ufuk Topcu, Joost-Pieter Katoen, Bernd Becker 0001 |
Abstraktions-basierte Verifikation von POMDPs im Motion-Planning-Kontext. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | |
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![Universität Tübingen, 978-3-00-059317-8 The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Timo Feld, Uwe Werkmann, Frank Slomka |
Real-Time Analysis of Distributed Systems including Tasks with Variable Rate-dependent Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
Towards Automated Refinement of TLM Properties to RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Philipp S. Käsgen, Markus Weinhardt |
Using Template Metaprogramming for Hardware Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Valentina Richthammer, Michael Glaß |
On Search-Space Restriction for Design Space Exploration of Multi-/Many-Core Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Florian Hock, Victor Pollex, Chijun Shen, Tobias Bund, Frank Slomka |
Upper Bound for Delay Densities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Tripti Jain, Klaus Schneider 0001 |
Routing Partial Permutations in General Interconnection Networks based on Radix Sorting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2018, Tübingen, Germany, February 8-9, 2018., 2018, Universität Tübingen, 978-3-00-059317-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
1 | Sebastian Simon, Jérôme Kirscher, Alexander W. Rath, Zhiqiang Zhang, Linus Maurer |
Pre-silicon Verification of an Automotive Battery Management System in the Context of the Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 91-102, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Saman Fröhlich, Daniel Große, Rolf Drechsler |
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 27-38, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Thiyagarajan Purusothaman, Christoph Grimm 0001 |
SystemC AMS based Co-simulation Framework for Cyber Physical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 55-66, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Amrutansh Gudivada, Daniel Kriesten, Ulrich Heinkel, Rene Röllig, Matthias Lenk |
OpenCL- Design Flow for High Level Synthesis and Cross-Platform Portability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 43-50, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Benjamin Beichler, Michael Rethfeldt, Hannes Raddatz, Björn Konieczek, Peter Danielis, Christian Haubelt, Dirk Timmermann |
Optimization of a novel WLAN Simulation Framework for Prototyping Network Applications and Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 15-26, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf |
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 103-114, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Hananeh Aliee, Abbas BanaiyanMofrad, Michael Glaß, Jürgen Teich, Nikil D. Dutt |
Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 1-12, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Heinz Riener, Rüdiger Ehlers, Görschwin Fey |
Counterexample-Guided EF Synthesis of Boolean Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 67-74, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Daniel Große, Rolf Drechsler (eds.) |
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![Shaker Verlag, 978-3-8440-4996-1 The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler |
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 75-78, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Hussam Amrouch, Jörg Henkel |
Containing Guardbands: From the Macro to Micro Time Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 13-14, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Christoph Grimm 0001, Carna Radojicic |
Extending Affine Arithmetic for Formal Verification of Analog/Mixed-Signal Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 39-40, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz |
Dynamic Power Optimization based on Formal Property Checking of Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 129-136, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Tobias Seufert, Christoph Scholl 0001 |
Sequential Verification Using Reverse PDR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 79-90, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Tobias Strauch |
A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 117-128, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz |
Speculative disassembly of binary code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 51-52, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille |
Verifikation von Networked Labs-on-Chip Architekturen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 41-42, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Ralf Stemmer, Maher Fakih |
Towards Timing and Power Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 115-116, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
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1 | Felix Neubauer, Karsten Scheibler, Bernd Becker 0001, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer |
Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 53-54, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
1 | Anoop Bhagyanath, Tripti Jain, Klaus Schneider 0001 |
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 77-88, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Schweizer, Murat Simsek, Oliver Bringmann 0001, Wolfgang Rosenstiel |
Eine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 59-71, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler |
Symbolic Error Metric Determination for Approximate Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 75-76, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ralf Wimmer 0001 |
Vorwort. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 4, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Thorsten Ropertz, Karsten Berns, Xian Li 0002, Klaus Schneider 0001 |
Verification of Behavior-Based Control Systems in their Physical Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 128-137, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Karsten Scheibler, Dominik Erb, Bernd Becker 0001 |
Applying Tailored Formal Methods to X-ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 138, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Christian Bartsch 0001, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz |
A HW-dependent Software Model for Cross-Layer Fault Analysis in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 10-21, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Christian Dehnert, Sebastian Junges, Nils Jansen 0001, Florian Corzilius, Matthias Volk 0001, Joost-Pieter Katoen, Erika Ábrahám, Harold Bruintjes |
Parameter Synthesis for Probabilistic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 72-74, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Dimitri Bohlender, Hendrik Simon, Stefan Kowalewski |
Symbolic Verification of PLC Safety-Applications based on PLCopen Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 33-45, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bo Wang 0010, Yang Xu 0019, Ralph Hasholzner, Christian Drewes, Rafael Rosales, Sebastian Graf 0002, Joachim Falk, Michael Glaß, Jürgen Teich |
Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 102-113, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Karina Wimmer |
Lösen von Booleschen Formeln mit Henkin-Quantoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 114-115, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jörg Walter 0001, Ralph Görgen, Wolfgang Nebel |
Predicting Performance and Energy Efficiency for Large-Scale Parallel Applications on Highly Heterogeneous Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 116-127, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sebastian Warsitz, Maher Fakih |
Simulink-Modell-Übersetzung in synchrone Datenflussgraphen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 89-101, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Tino Teige, Tom Bienmüller, Hans Jürgen Holberg |
Universal Pattern: Formalization, Testing, Coverage, Verification, and Test Case Generation for Safety-Critical Requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 6-9, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Carsten Schmitt, Christoph Jäschke, Claudia Wolkober, Ulla Herter |
Connecting a C++ based Structural Verification Tool to the Web. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 22-32, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ralf Wimmer 0001 (eds.) |
19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9 The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
1 | Andy Sauter, Joachim Gerlach |
Simulationsbasierte Analyse energietechnischer Systemszenarien. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 139-150, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Konstantin Lübeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, Oliver Bringmann 0001 |
Neues Konzept zur Steigerung der Zuverlässigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2016, Freiburg im Breisgau, Germany, March 1-2, 2016., pp. 46-58, 2016, Albert-Ludwigs-Universität Freiburg, 978-3-00-052380-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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1 | Christian Schott, Marko Rößler, Ulrich Heinkel |
Verfahren zur Assertion basierten Verifikation bei der High-Level-Synthese. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015., pp. 5-13, 2015, Sächsische Landesbibliothek, 978-3-00-048889-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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1 | Aquib Rashid, Wolfram Hardt |
HOPE: Hardware Optimized Parallel Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015., pp. 155-159, 2015, Sächsische Landesbibliothek, 978-3-00-048889-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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1 | Thilo Vörtler, Benny Höckner, Petra Hofstedt, Thomas Klotz |
Formale Verifikation von eingebetteter Software für das Betriebssystem Contiki unter Berücksichtigung von Interrupts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015., pp. 20-29, 2015, Sächsische Landesbibliothek, 978-3-00-048889-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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1 | Karsten Scheibler, Leonore Winterer, Ralf Wimmer 0001, Bernd Becker 0001 |
Towards Verification of Artificial Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015., pp. 30-40, 2015, Sächsische Landesbibliothek, 978-3-00-048889-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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