Search results for "MEDEA@PACT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki J. Murakami	Performance balancing: software-based on-chip memory management for effective CMP executions.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Devesh Tiwari, Sanghoon Lee 0006, James Tuck 0001, Yan Solihin	Memory management thread for heap allocation intensive sequential applications.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete (eds.)	Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Susmit Biswas, Diana Franklin, Timothy Sherwood, Frederic T. Chong, Bronis R. de Supinski, Martin Schulz 0001	PSMalloc: content based memory management for MPI applications.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Yoshiei Sato, Ryu-ichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi	Performance tuning and analysis of future vector processors based on the roofline model.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Mostafa Farahani, Amirali Baniasadi	Temperature reduction analysis in Sentry Tag cache systems.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Roger Ferrer, Vicenç Beltran 0001, Marc González 0001, Xavier Martorell, Eduard Ayguadé	Achieving high memory performance from heterogeneous architectures with the SARC programming model.	MEDEA@PACT	2009	DBLP DOI BibTeX RDF
1	Layali K. Rashid, Wessam M. Hassanein, Moustafa A. Hammad	Exploiting multithreaded architectures to improve the hash join operation.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Mafijul Md. Islam, Per Stenström	Zero loads: canceling load requests by tracking zero values.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Roger Ferrer, Marc González 0001, Federico Silla, Xavier Martorell, Eduard Ayguadé	Evaluation of memory performance on the cell BE with the SARC programming model.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Jaydeep Marathe, Frank Mueller 0001	PFetch: software prefetching exploiting temporal predictability of memory access streams.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi (eds.)	Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	Modeling of cache access behavior based on Zipf's law.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer	Predictable dynamic instruction scratchpad for simultaneous multithreaded processors.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A shared cache for a chip multi vector processor.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Hyunhee Kim, Sungjun Youn, Jihong Kim 0001	A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Marc Lupon, Grigorios Magklis, Antonio González 0001	Version management alternatives for hardware transactional memory.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Mitchell Hayenga, Chander Sudanthi, Mrinmoy Ghosh, Prakash Ramrakhyani, Nigel C. Paver	Accurate system-level performance modeling and workload characterization for mobile internet devices.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Ferad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris 0001	WormBench: a configurable workload for evaluating transactional memory systems.	MEDEA@PACT	2008	DBLP DOI BibTeX RDF
1	Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Mohammed Fellahi, Albert Cohen 0001, Sid Ahmed Ali Touati	Code-size conscious pipelining of imperfectly nested loops.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Paolo Bennati	Reducing leakage in power-saving capable caches for embedded systems by using a filter cache.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Akihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada	Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi (eds.)	Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero	Multithreaded software transactional memory and OpenMP.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Tarik Saidani, Stéphane Piskorski, Lionel Lacassagne, Samir Bouaziz	Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithm.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Valentina Salapura, Matthias A. Blumrich, Alan Gara	Improving the accuracy of snoop filtering using stream registers.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Analysis of static and dynamic energy consumption in NUCA caches: initial results.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Vicenç Beltran 0001, Jordi Torres, Eduard Ayguadé	Improving disk bandwidth-bound applications through main memory compression.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Chun-Mok Chung, Jihong Kim 0001	Broadcast filtering-aware task assignment techniques for low-power MPSoCs.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström, José María Llabería	Characterization of Apache web server with Specweb2005.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Gabriel Tanase, Mauro Bianco, Nancy M. Amato, Lawrence Rauchwerger	The STAPL pArray.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Akihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi	An on-chip cache design for vector processors.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Fernando Latorre, Grigorios Magklis, José González 0002, Pedro Chaparro, Antonio González 0001	Building a large instruction window through ROB compression.	MEDEA@PACT	2007	DBLP DOI BibTeX RDF
1	Jun Yan, Wei Zhang	Evaluating instruction cache vulnerability to transient errors.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals	Data prefetching in a cache hierarchy with high bandwidth and capacity.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	A simple speculative load control mechanism for energy saving.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	K. Patrick Lorton, David S. Wise	Analyzing block locality in Morton-order and Morton-hybrid matrices.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	Kaveh Jokar Deris, Amirali Baniasadi	Investigating cache energy and latency break-even points in high performance processors.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1		Proceedings of the 2006 workshop on MEmory performance - DEaling with Applications, systems and architectures, MEDEA '06, Seattle, Washington, USA, September 16-20, 2006	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	Haakon Dybdahl, Per Stenström, Lasse Natvig	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.	MEDEA@PACT	2006	DBLP DOI BibTeX RDF
1	Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete (eds.)	Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Hyo-Joong Suh, Sung Woo Chung	DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Sami Yehia, Jean-Francois Collard, Olivier Temam	Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Afrin Naz, Mehran Rezaei, Krishna Kavi, Philip H. Sweany	Improving data cache performance with integrated use of split caches, victim cache and stream buffers.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin	Energy aware memory architecture configuration.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero	The impact of traffic aggregation on the memory performance of networking applications.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa	Locality analysis to control dynamically way-adaptable caches.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative execution for hiding memory latency.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1		Guests editor's introduction.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF
1	Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori	SH-X: an embedded processor core for consumer appliances.	MEDEA@PACT	2004	DBLP DOI BibTeX RDF

Publications at "MEDEA@PACT"( http://dblp.L3S.de/Venues/MEDEA@PACT )