| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chung-Kuan Cheng, Bill Lin 0001, Byeonggon Kang, Yucheng Wang |
Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies.  |
SLIP  |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Arghavan Mohammadhassani, Anup Das 0001 |
Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM. |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin 0001, Yucheng Wang, Dooseok Yoon |
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration. |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Raveena Raikar, Dirk Stroobandt |
Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures. |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Marieke Louage, Muhammad Mazher Iqbal, Dirk Stroobandt |
On the Interconnection Complexity vs Size Trade-off in Circuit Graphs. |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | Seonghyeon Park, Daeyeon Kim, Seokhyeong Kang |
Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization. |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | |
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, SLIP 2023, San Francisco, CA, USA, 2 November 2023 |
SLIP |
2023 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Philippe, Lorenzo Ciampolini, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël |
An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Raveena Raikar, Dirk Stroobandt |
Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning be? |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne |
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Tianyi Yu, Nima Karimpour Darav, Ismail Bustany, Mehrdad Eslami Dehkordi |
A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA's. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Hailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, Ismail Bustany |
Machine-Learning Based Delay Prediction for FPGA Technology Mapping. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaehoon Ahn, Taewhan Kim |
Neural Network Model for Detour Net Prediction. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustafa Badaroglu, Shantanu Dutt (eds.) |
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022 |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiuyan Zhang, Shantanu Dutt |
Limiting Interconnect Heating in Power-Driven Physical Synthesis. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
| 1 | Babak Sharifpour, Mohammad Sharifpour, Midia Reshadi |
SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Suresh Ramalingam |
Enabling Chiplet Integration Beyond 7nm (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jitesh Choudhary, Soumya J., Linga Reddy Cenkeramaddi |
RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Minmin Jiang, Vasilis F. Pavlidis |
Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes |
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic |
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Yvain Thonnart |
Designing a Multi-Chiplet Manycore System using the POPSTAR Optical NoC Architecture (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Tanay Karnik |
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiago Mück |
Network-on-Chips for Future 3D Stacked Dies (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Bapi Vinnakota |
The Open Domain-Specific Architecture: An Introduction (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | |
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2021, Munich, Germany, November 4, 2021 |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Makoto Nagata |
Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin 0001 |
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanna Calò, Marina Barbiroli, Gaetano Bellanca, Davide Bertozzi, Franco Fuschini, Velio Tralli, Giovanni Serafino, Vincenzo Petruzzelli |
Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Joris Van Campenhout |
Silicon Photonics Technology for Terabit-scale Optical I/O (Invited). |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonathan D'Hoore, Poona Bahrebar, Dirk Stroobandt |
3D NoC emulation model on a single FPGA. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Raid Ayoub, Michael Kishinevsky, Sumit K. Mandal, Ümit Y. Ogras |
Analytical modeling of NoCs for fast simulation and design exploration (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tahereh Jabbari, Eby G. Friedman |
Global interconnects in VLSI complexity single flux quantum systems. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Kumar Jain |
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng (eds.) |
SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020 |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez |
Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Groeneveld |
Wafer scale interconnect and pathfinding for machine learning hardware (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Saptadeep Pal, Puneet Gupta 0001 |
Pathfinding for 2.5D interconnect technologies. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustafa Badaroglu |
Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Kauth, Tim Stadtmann, Ruben Brandhofer, Vida Sobhani, Tobias Gemmeke |
Communication architecture enabling 100x accelerated simulation of biological neural networks. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuck-Boon Chan, Andrew B. Kahng, Mingyu Woo |
Revisiting inherent noise floors for interconnect prediction. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Orcutt |
Extending quantum systems with optical interconnects (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Barry C. Sanders |
Building a quantum computer (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | |
21st ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2019, Las Vegas, NV, USA, June 1-2, 2019 |
SLIP |
2019 |
DBLP BibTeX RDF |
|
| 1 | Zheng Xu, Jacob Abraham |
FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young |
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Boris Vaisband, Subramanian S. Iyer |
Communication Considerations for Silicon Interconnect Fabric. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Farid Kenarangi, Inna Partin-Vaisband |
Security Network On-Chip for Mitigating Side-Channel Attacks. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Dylan C. Stow, Itir Akgun, Yuan Xie 0001 |
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Ali Vosoughi, Longfei Wang, Selçuk Köse |
Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiming Wen, Sayyed Farid Ahamed, Weize Yu |
A Novel PUF Architecture Against Non-Invasive Attacks. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Longfei Wang, Ragh Kuttappa, Baris Taskin, Selçuk Köse |
Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Leo Filippini, Baris Taskin |
A charge recovery logic system bus. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Isuru Daulagala, Ioannis Savidis |
Clock tree synthesis for heterogeneous 3-D integrated circuits. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | |
ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017 |
SLIP |
2017 |
DBLP BibTeX RDF |
|
| 1 | Scott Lerner, Eric Leggett, Baris Taskin |
Slew-down: analysis of slew relaxation for low-impact clock buffers. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ulf Schlichtmann |
Frontiers of timing. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wing-Kai Chow, Jian Kuang 0001, Peishan Tu, Evangeline F. Y. Young |
Fence-aware detailed-routability driven placement. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha |
Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young |
Timing driven routing tree construction. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen 0001 |
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. |
SLIP |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto |
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Roman P. Bazylevych, Marek Palasinski, Lubov Bazylevych |
Topologically-Geometric Routing. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske |
Buffered Interconnects in 3D IC Layout Design. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Carrie Segal, Aditya Dalakoti, Merritt Miller, Forrest Brewer |
Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li 0002 |
Revisiting 3DIC Benefit with Multiple Tiers. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Naseef Mansoor, Md Shahriar Shamim, Amlan Ganguly |
A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Ishan G. Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha |
A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001 |
Spin-Hall Assisted STT-RAM Design and Discussion. |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Baris Taskin, Tsung-Yi Ho (eds.) |
Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016 |
SLIP |
2016 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Martin D. F. Wong |
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Sai Manoj P. D., Kanwen Wang, Hantao Huang, Hao Yu 0001 |
Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Ümit Y. Ogras, Kambiz Samadi |
Multi-product floorplan and uncore design framework for chip multiprocessors. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | |
2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015, San Francisco, CA, USA, June 6, 2015 |
SLIP |
2015 |
DBLP BibTeX RDF |
|
| 1 | Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas |
Clock clustering and IO optimization for 3D integration. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Mulong Luo, Siddhartha Nath |
SI for free: machine learning of interconnect coupling delay and transition effects. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Zhang, Yang Liu, Ryan Coutts, Chung-Kuan Cheng |
Power line communication for hybrid power/signal pin SOC design. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Haifeng Xu, Melissa M. Bilec, William O. Collinge, Laura A. Schaefer, Amy E. Landis, Alex K. Jones |
Lynx: a self-organizing wireless sensor network with commodity palmtop computers. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Wu 0008, Chin-Hui Chen, Jean-Marc Fedeli, Maryse Fournier, Raymond G. Beausoleil, Kwang-Ting Cheng |
Compact modeling and system implications of microring modulators in nanophotonic interconnects. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath |
Methodology for electromigration signoff in the presence of adaptive voltage scaling. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiaosha Zou, Yuan Xie 0001 |
Compact models and model standard for 2.5D and 3D integration. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | |
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2014, San Francisco, CA, USA, June 1, 2014 |
SLIP |
2014 |
DBLP BibTeX RDF |
|
| 1 | Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li 0001, Charles J. Alpert, Cliff C. N. Sze |
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng |
Worst-case noise area prediciton of on-chip power distribution network. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Julian Kemmerer, Baris Taskin |
Range-based dynamic routing of hierarchical on chip network traffic. |
SLIP |
2014 |
DBLP BibTeX RDF |
|
| 1 | Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong |
UI-route: An ultra-fast incremental maze routing algorithm. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Inna Vaisband, Eby G. Friedman |
Power network-on-chip for scalable power delivery. |
SLIP |
2014 |
DBLP DOI BibTeX RDF |
|
| 1 | Rasit Onur Topaloglu |
Chip-scale physical interconnect models (Tutorial). |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Bill Lin 0001, Siddhartha Nath |
High-dimensional metamodeling for prediction of clock tree synthesis outcomes. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Randy Morris, Avinash Karanth Kodi, Ahmed Louri |
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Condrat, Priyank Kalla, Steve Blair |
Channel routing for integrated optics. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Doug Gill |
IBM CMOS compatible photonics and traveling wave electro-optic modulator design. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li 0002 |
Toward quantifying the IC design value of interconnect technology improvements. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaloo Rakheja, Vachan Kumar, Azad Naeemi |
Performance modeling for interconnects for conventional and emerging switches. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Deming Chen |
Optimizations in GPU: Smart compilers and core-level reconfiguration. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Baris Taskin |
Wireless on Networks-on-Chip. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark Browning, Cheng Li, Paul V. Gratz, Samuel Palermo |
LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Seokhyeong Kang, Hyein Lee 0001, Siddhartha Nath, Jyoti Wadhwani |
Learning-based approximation of interconnect delay and slew in signoff timing tools. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
| 1 | |
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, USA, June 2, 2013 |
SLIP |
2013 |
DBLP BibTeX RDF |
|
| 1 | Xiang Zhang, Yang Liu, Chung-Kuan Cheng |
Worst-case noise prediction using power network impedance profile. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
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