Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Florent Autrusseau, Yves Amouriq, Jean-Pierre Guédon	Linking bone microarchitecture to projections texture analysis.	Medical Imaging: Biomedical Applications in Molecular, Structural, and Functional Imaging	2016	DBLP DOI BibTeX RDF
17	Remberto Sandoval-Arechiga, Ramón Parra-Michel, J. L. Vázquez-Avila, B. I. Gea-Garcia	NI + Router Microarchitecture for NoC-based Communication Systems.	ANCS	2016	DBLP DOI BibTeX RDF
17	Shibo Wang, Engin Ipek	Reducing data movement energy via online data clustering and encoding.	MICRO	2016	DBLP DOI BibTeX RDF
17	Elvira Teran, Zhe Wang 0023, Daniel A. Jiménez	Perceptron learning for reuse prediction.	MICRO	2016	DBLP DOI BibTeX RDF
17	Muhammad Husni Santriaji, Henry Hoffmann	GRAPE: Minimizing energy for GPU applications with performance requirements.	MICRO	2016	DBLP DOI BibTeX RDF
17	Li-Wen Chang, Izzat El Hajj, Christopher I. Rodrigues, Juan Gómez-Luna, Wen-mei W. Hwu	Efficient kernel synthesis for performance portable programming.	MICRO	2016	DBLP DOI BibTeX RDF
17	Cheng-Chieh Huang, Rakesh Kumar 0003, Marco Elver, Boris Grot, Vijay Nagarajan	C3D: Mitigating the NUMA bottleneck via coherent DRAM caches.	MICRO	2016	DBLP DOI BibTeX RDF
17	Yang Hu 0001, Tao Li 0006	Towards efficient server architecture for virtualized network function deployment: Implications and implementations.	MICRO	2016	DBLP DOI BibTeX RDF
17	Alberto Ros 0001, Stefanos Kaxiras	Racer: TSO consistency via race detection.	MICRO	2016	DBLP DOI BibTeX RDF
17	Hardik Sharma, Jongse Park, Divya Mahajan 0001, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, Hadi Esmaeilzadeh	From high-level deep neural models to FPGAs.	MICRO	2016	DBLP DOI BibTeX RDF
17	Arthur Perais, Fernando A. Endo, André Seznec	Register sharing for equality prediction.	MICRO	2016	DBLP DOI BibTeX RDF
17	Amirali Sharifian, Snehasish Kumar, Apala Guha, Arrvindh Shriraman	Chainsaw: Von-neumann accelerators to leverage fused instruction chains.	MICRO	2016	DBLP DOI BibTeX RDF
17	Tao Chen 0045, G. Edward Suh	Efficient data supply for hardware accelerators with prefetching and access/execute decoupling.	MICRO	2016	DBLP DOI BibTeX RDF
17	Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz	Improving energy efficiency of DRAM by exploiting half page row access.	MICRO	2016	DBLP DOI BibTeX RDF
17	Manoj Alwani, Han Chen, Michael Ferdman, Peter A. Milder	Fused-layer CNN accelerators.	MICRO	2016	DBLP DOI BibTeX RDF
17	Mengjia Yan 0001, Yasser Shalabi, Josep Torrellas	ReplayConfusion: Detecting cache-based covert channel attacks using record and replay.	MICRO	2016	DBLP DOI BibTeX RDF
17	Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari	Quantifying and improving the efficiency of hardware-based mobile malware detectors.	MICRO	2016	DBLP DOI BibTeX RDF
17	Tae Jun Ham, Lisa Wu 0001, Narayanan Sundaram, Nadathur Satish, Margaret Martonosi	Graphicionado: A high-performance and energy-efficient accelerator for graph analytics.	MICRO	2016	DBLP DOI BibTeX RDF
17	Kaige Yan, Xingyao Zhang, Jingweijia Tan, Xin Fu	Redefining QoS and customizing the power management policy to satisfy individual mobile users.	MICRO	2016	DBLP DOI BibTeX RDF
17	Yu Ji 0002, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie 0001, Wenguang Chen	NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.	MICRO	2016	DBLP DOI BibTeX RDF
17	Stephen Zekany, Daniel Rings, Nathan Harada, Michael A. Laurenzano, Lingjia Tang, Jason Mars	CrystalBall: Statically analyzing runtime behavior via deep sequence learning.	MICRO	2016	DBLP DOI BibTeX RDF
17	Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh	Jump over ASLR: Attacking branch predictors to bypass ASLR.	MICRO	2016	DBLP DOI BibTeX RDF
17	Biswabandan Panda, André Seznec	Dictionary sharing: An efficient cache compression scheme for compressed caches.	MICRO	2016	DBLP DOI BibTeX RDF
17	Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang 0002, Chao Li 0009, Xiaoyao Liang	Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.	MICRO	2016	DBLP DOI BibTeX RDF
17	Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler	A patch memory system for image processing and computer vision.	MICRO	2016	DBLP DOI BibTeX RDF
17	Izzat El Hajj, Juan Gómez-Luna, Cheng Li 0014, Li-Wen Chang, Dejan S. Milojicic, Wen-mei W. Hwu	KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism.	MICRO	2016	DBLP DOI BibTeX RDF
17	Animesh Jain, Michael A. Laurenzano, Lingjia Tang, Jason Mars	Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting.	MICRO	2016	DBLP DOI BibTeX RDF
17	Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler	vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design.	MICRO	2016	DBLP DOI BibTeX RDF
17	Johnathan Alsop, Marc S. Orr, Bradford M. Beckmann, David A. Wood 0001	Lazy release consistency for GPUs.	MICRO	2016	DBLP DOI BibTeX RDF
17	Vaibhav Gogte, Aasheesh Kolli, Michael J. Cafarella, Loris D'Antoni, Thomas F. Wenisch	HARE: Hardware accelerator for regular expressions.	MICRO	2016	DBLP DOI BibTeX RDF
17	Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie 0001	A unified memory network architecture for in-memory computing in commodity servers.	MICRO	2016	DBLP DOI BibTeX RDF
17	Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz	Evaluating programmable architectures for imaging and vision applications.	MICRO	2016	DBLP DOI BibTeX RDF
17	Qingrui Liu, Changhee Jung, Dongyoon Lee, Devesh Tiwari	Low-cost soft error resilience with unified data verification and fine-grained recovery for acoustic sensor based detection.	MICRO	2016	DBLP DOI BibTeX RDF
17	Renhai Chen, Zili Shao, Tao Li 0006	Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach.	MICRO	2016	DBLP DOI BibTeX RDF
17	Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim 0001, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, Doug Burger	A cloud-scale acceleration architecture.	MICRO	2016	DBLP DOI BibTeX RDF
17	Yazhou Zu, Wei Huang 0004, Indrani Paul, Vijay Janapa Reddi	Ti-states: Processor power management in the temperature inversion region.	MICRO	2016	DBLP DOI BibTeX RDF
17	Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks	Co-designing accelerators and SoC interfaces using gem5-Aladdin.	MICRO	2016	DBLP DOI BibTeX RDF
17	Ahmed ElTantawy, Tor M. Aamodt	MIMD synchronization on SIMT architectures.	MICRO	2016	DBLP DOI BibTeX RDF
17	Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Manabi Khan, Ashish Shrestha, Saugata Ghose, Adwait Jog, Phillip B. Gibbons, Onur Mutlu	Zorua: A holistic approach to resource virtualization in GPUs.	MICRO	2016	DBLP DOI BibTeX RDF
17	Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali G. Saidi, Steven Pelley, Sihang Liu 0001, Peter M. Chen, Thomas F. Wenisch	Delegated persist ordering.	MICRO	2016	DBLP DOI BibTeX RDF
17	Gwangsun Kim, Changhyun Kim, Jiyun Jeong, Mike Parker, John Kim	Contention-based congestion management in large-scale networks.	MICRO	2016	DBLP DOI BibTeX RDF
17	Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi	CANDY: Enabling coherent DRAM caches for multi-node systems.	MICRO	2016	DBLP DOI BibTeX RDF
17	Dimitrios Skarlatos 0002, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas	Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.	MICRO	2016	DBLP DOI BibTeX RDF
17	Milad Hashemi, Onur Mutlu, Yale N. Patt	Continuous runahead: Transparent hardware acceleration for memory intensive workloads.	MICRO	2016	DBLP DOI BibTeX RDF
17	Nader Sehatbakhsh, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic	Spectral profiling: Observer-effect-free profiling by monitoring EM emanations.	MICRO	2016	DBLP DOI BibTeX RDF
17	Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie 0001	OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures.	MICRO	2016	DBLP DOI BibTeX RDF
17	Guowei Zhang 0002, Virginia Chiu, Daniel Sánchez 0003	Exploiting semantic commutativity in hardware speculation.	MICRO	2016	DBLP DOI BibTeX RDF
17	Shijin Zhang, Zidong Du, Lei Zhang 0008, Huiying Lan, Shaoli Liu, Ling Li 0001, Qi Guo 0001, Tianshi Chen 0002, Yunji Chen	Cambricon-X: An accelerator for sparse neural networks.	MICRO	2016	DBLP DOI BibTeX RDF
17	Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee	PoisonIvy: Safe speculation for secure memory.	MICRO	2016	DBLP DOI BibTeX RDF
17	Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Andreas Moshovos	Stripes: Bit-serial deep neural network computing.	MICRO	2016	DBLP DOI BibTeX RDF
17	Reza Yazdani, Albert Segura, José-María Arnau, Antonio González 0001	An ultra low-power hardware accelerator for automatic speech recognition.	MICRO	2016	DBLP DOI BibTeX RDF
17	Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez 0003	Data-centric execution of speculative parallel programs.	MICRO	2016	DBLP DOI BibTeX RDF
17	Margaret Martonosi	Keynotes: Internet of Things: History and hype, technology and policy.	MICRO	2016	DBLP DOI BibTeX RDF
17	Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim	Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems.	MICRO	2016	DBLP DOI BibTeX RDF
17	Animesh Jain, Parker Hill, Shih-Chieh Lin, Muneeb Khan, Md. Enamul Haque, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars	Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation.	MICRO	2016	DBLP DOI BibTeX RDF
17	Alexandros Daglis, Dmitrii Ustiugov, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot	SABRes: Atomic object reads for in-memory rack-scale computing.	MICRO	2016	DBLP DOI BibTeX RDF
17	Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti	Path confidence based lookahead prefetching.	MICRO	2016	DBLP DOI BibTeX RDF
17	Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel	The Bunker Cache for spatio-value approximation.	MICRO	2016	DBLP DOI BibTeX RDF
17	Yonatan Gottesman, Yoav Etsion	NeSC: Self-virtualizing nested storage controller.	MICRO	2016	DBLP DOI BibTeX RDF
17	Xulong Tang, Mahmut T. Kandemir, Praveen Yedlapalli, Jagadish Kotra	Improving bank-level parallelism for irregular applications.	MICRO	2016	DBLP DOI BibTeX RDF
17	Radha Venkatagiri, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Sarita V. Adve	Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency.	MICRO	2016	DBLP DOI BibTeX RDF
17	Prathmesh Kallurkar, Smruti R. Sarangi	pTask: A smart prefetching scheme for OS intensive applications.	MICRO	2016	DBLP DOI BibTeX RDF
17	Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri	Dynamic error mitigation in NoCs using intelligent prediction techniques.	MICRO	2016	DBLP DOI BibTeX RDF
17	Trevor E. Carlson, Siddharth Nilakantan, Mark Hempstead, Wim Heirman	Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.	IEEE Comput. Archit. Lett.	2015	DBLP DOI BibTeX RDF
17	Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono	Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.	Int. J. Reconfigurable Comput.	2015	DBLP DOI BibTeX RDF
17	Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler	IBM POWER8 processor core microarchitecture.	IBM J. Res. Dev.	2015	DBLP DOI BibTeX RDF
17	Pierre Michaud, Andrea Mondelli, André Seznec	Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters.	ACM Trans. Archit. Code Optim.	2015	DBLP DOI BibTeX RDF
17	Johannes Hofmann 0001, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein	Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks.	CoRR	2015	DBLP BibTeX RDF
17	Alexandra Hotca, Shreyas Ravichandra, Artem Mikheev, Henry Rusinek, Gregory Chang	Precision of volumetric assessment of proximal femur microarchitecture from high-resolution 3T MRI.	Int. J. Comput. Assist. Radiol. Surg.	2015	DBLP DOI BibTeX RDF
17	Milos Prvulovic (eds.)	Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015	MICRO	2015	DBLP DOI BibTeX RDF
17	Arnaud Lefray, Eddy Caron, Jonathan Rouzaud-Cornabas, Christian Toinard	Microarchitecture-Aware Virtual Machine Placement under Information Leakage Constraints.	CLOUD	2015	DBLP DOI BibTeX RDF
17	Libo Huang, Yongwen Wang, Qiang Dou, Chengyi Zhang, Caixia Sun, Chao Xu	Fast FPGA system for microarchitecture optimization on synthesizable modern processor design.	FPL	2015	DBLP DOI BibTeX RDF
17	Chen-Han Ho, Venkatraman Govindaraju, Tony Nowatzki, Ranjini Nagaraju, Zachary Marzec, Preeti Agarwal, Chris Frericks, Ryan Cofell, Karthikeyan Sankaralingam	Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation.	ISPASS	2015	DBLP DOI BibTeX RDF
17	Kaisheng Ma, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan	Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.	ICCAD	2015	DBLP DOI BibTeX RDF
17	Biruk Mammo, Ritesh Parikh, Valeria Bertacco	ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability.	ISLPED	2015	DBLP DOI BibTeX RDF
17	Garo Bournoutian, Alex Orailoglu	Mobile ecosystem driven application-specific low-power control microarchitecture.	ICCD	2015	DBLP DOI BibTeX RDF
17	Satish Kumar Sadasivam, S. Thamarai Selvi	Performance evaluation of Data Mining algorithms on three generations of Intel® microarchitecture.	HPCS	2015	DBLP DOI BibTeX RDF
17	Trevor E. Carlson, Wim Heirman, Osman Allam, Stefanos Kaxiras, Lieven Eeckhout	The load slice core microarchitecture.	ISCA	2015	DBLP DOI BibTeX RDF
17	Jiwei Liu, Jun Yang 0002, Rami G. Melhem	SAWS: synchronization aware GPGPU warp scheduling for multiple independent warp schedulers.	MICRO	2015	DBLP DOI BibTeX RDF
17	Harshad Kasture, Davide B. Bartolini, Nathan Beckmann, Daniel Sánchez 0003	Rubik: fast analytical power management for latency-critical systems.	MICRO	2015	DBLP DOI BibTeX RDF
17	Daniel Lo, Taejoon Song, G. Edward Suh	Prediction-guided performance-energy trade-off for interactive applications.	MICRO	2015	DBLP DOI BibTeX RDF
17	Angelos Arelakis, Fredrik Dahlgren, Per Stenström	HyComp: a hybrid cache compression method for selection of data-type-specific compression methods.	MICRO	2015	DBLP DOI BibTeX RDF
17	Yanwei Song, Engin Ipek	More is less: improving the energy efficiency of data movement via opportunistic use of sparse codes.	MICRO	2015	DBLP DOI BibTeX RDF
17	Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti	Efficiently prefetching complex address patterns.	MICRO	2015	DBLP DOI BibTeX RDF
17	Lena E. Olson, Jason Power, Mark D. Hill, David A. Wood 0001	Border control: sandboxing accelerators.	MICRO	2015	DBLP DOI BibTeX RDF
17	William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin	Locking down insecure indirection with hardware-based control-data isolation.	MICRO	2015	DBLP DOI BibTeX RDF
17	Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran, Pradip Bose, Vijay Janapa Reddi	Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach.	MICRO	2015	DBLP DOI BibTeX RDF
17	Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud	Long term parking (LTP): criticality-aware resource allocation in OOO processors.	MICRO	2015	DBLP DOI BibTeX RDF
17	Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa, Antonio González 0001	Ultra-low power render-based collision detection for CPU/GPU systems.	MICRO	2015	DBLP DOI BibTeX RDF
17	Dani Voitsechov, Yoav Etsion	Control flow coalescing on a hybrid dataflow/von Neumann GPGPU.	MICRO	2015	DBLP DOI BibTeX RDF
17	Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh	Enabling interposer-based disintegration of multi-core processors.	MICRO	2015	DBLP DOI BibTeX RDF
17	Daniel S. McFarlin, Craig B. Zilles	Bungee jumps: accelerating indirect branches through HW/SW co-design.	MICRO	2015	DBLP DOI BibTeX RDF
17	Yuhao Zhu 0001, Daniel Richins, Matthew Halpern, Vijay Janapa Reddi	Microarchitectural implications of event-driven server-side web applications.	MICRO	2015	DBLP DOI BibTeX RDF
17	Tao Chen 0045, Alexander Rucker, G. Edward Suh	Execution time prediction for energy-efficient hardware accelerators.	MICRO	2015	DBLP DOI BibTeX RDF
17	Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien	Fast support for unstructured data processing: the unified automata processor.	MICRO	2015	DBLP DOI BibTeX RDF
17	Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry	Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses.	MICRO	2015	DBLP DOI BibTeX RDF
17	Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Srinivas Devadas	IMP: indirect memory prefetcher.	MICRO	2015	DBLP DOI BibTeX RDF
17	Guowei Zhang 0002, Webb Horn, Daniel Sánchez 0003	Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems.	MICRO	2015	DBLP DOI BibTeX RDF
17	Daehoon Kim, Hwanju Kim, Nam Sung Kim, Jaehyuk Huh 0001	vCache: architectural support for transparent and isolated virtual LLCs in virtualized environments.	MICRO	2015	DBLP DOI BibTeX RDF
17	Guoyang Chen, Xipeng Shen	Free launch: optimizing GPU dynamic kernel launches through thread reuse.	MICRO	2015	DBLP DOI BibTeX RDF