Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Erich Wenger, Johann Großschädl	An 8-bit AVR-Based Elliptic Curve Cryptographic RISC Processor for the Internet of Things.	MICRO Workshops	2012	DBLP DOI BibTeX RDF
17	Wei Huang 0004, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael S. Floyd, Karthick Rajamani, Malcolm Allen-Ware, Bishop Brock	Accurate Fine-Grained Processor Power Proxies.	MICRO	2012	DBLP DOI BibTeX RDF
17	Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke	Composite Cores: Pushing Heterogeneity Into a Core.	MICRO	2012	DBLP DOI BibTeX RDF
17	Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu	Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.	MICRO	2012	DBLP DOI BibTeX RDF
17	Randy Morris, Avinash Karanth Kodi, Ahmed Louri	Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance.	MICRO	2012	DBLP DOI BibTeX RDF
17	Daniel Wong 0001, Murali Annavaram	KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity.	MICRO	2012	DBLP DOI BibTeX RDF
17	Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael J. Schulte, William Lloyd Bircher, Madhu Saravana Sibi Govindan	AUDIT: Stress Testing the Automatic Way.	MICRO	2012	DBLP DOI BibTeX RDF
17	Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla	Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem.	MICRO	2012	DBLP DOI BibTeX RDF
17	Weidan Wu, Benjamin C. Lee	Inferred Models for Dynamic and Sparse Hardware-Software Spaces.	MICRO	2012	DBLP DOI BibTeX RDF
17	Lizhong Chen, Timothy Mark Pinkston	NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers.	MICRO	2012	DBLP DOI BibTeX RDF
17	Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally	Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.	MICRO	2012	DBLP DOI BibTeX RDF
17	Christian Jacobi 0002, Timothy J. Slegel, Dan F. Greiner	Transactional Memory Architecture and Implementation for IBM System Z.	MICRO	2012	DBLP DOI BibTeX RDF
17	Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini	CoScale: Coordinating CPU and Memory System DVFS in Server Systems.	MICRO	2012	DBLP DOI BibTeX RDF
17	Socrates Demetriades, Sangyeun Cho	Predicting Coherence Communication by Tracking Synchronization Points at Run Time.	MICRO	2012	DBLP DOI BibTeX RDF
17	Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas, Lesley Shannon	Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy.	MICRO	2012	DBLP DOI BibTeX RDF
17	Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger	Neural Acceleration for General-Purpose Approximate Programs.	MICRO	2012	DBLP DOI BibTeX RDF
17	Hyeran Jeon, Murali Annavaram	Warped-DMR: Light-weight Error Detection for GPGPU.	MICRO	2012	DBLP DOI BibTeX RDF
17	Abdullah Muzahid, Shanxiang Qi, Josep Torrellas	Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically.	MICRO	2012	DBLP DOI BibTeX RDF
17	Alain Ketterlin, Philippe Clauss	Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization.	MICRO	2012	DBLP DOI BibTeX RDF
17	Mohammad Alisafaee	Spatiotemporal Coherence Tracking.	MICRO	2012	DBLP DOI BibTeX RDF
17	Lei Jiang 0001, Youtao Zhang, Bruce R. Childers, Jun Yang 0002	FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.	MICRO	2012	DBLP DOI BibTeX RDF
17	Binh Pham 0003, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee	CoLT: Coalesced Large-Reach TLBs.	MICRO	2012	DBLP DOI BibTeX RDF
17	Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo 0001, Benjamin C. Lee, Mark Horowitz	Rethinking DRAM Power Modes for Energy Proportionality.	MICRO	2012	DBLP DOI BibTeX RDF
17	Pejman Lotfi-Kamran, Boris Grot, Babak Falsafi	NOC-Out: Microarchitecting a Scale-Out Processor.	MICRO	2012	DBLP DOI BibTeX RDF
17	Yongjun Park 0001, Jason Jong Kyu Park, Hyunchul Park 0001, Scott A. Mahlke	Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability.	MICRO	2012	DBLP DOI BibTeX RDF
17	Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt	Cache-Conscious Wavefront Scheduling.	MICRO	2012	DBLP DOI BibTeX RDF
17	Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum	Improving Cache Management Policies Using Dynamic Reuse Distances.	MICRO	2012	DBLP DOI BibTeX RDF
17	Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili	Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation.	MICRO	2012	DBLP DOI BibTeX RDF
17	Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang 0002, Ramesh Illikkal, Ravi R. Iyer 0001	Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.	MICRO	2012	DBLP DOI BibTeX RDF
17	Cheng Wang 0013, Youfeng Wu, Hongbo Rong, Hyunchul Park	SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations.	MICRO	2012	DBLP DOI BibTeX RDF
17	Islam Atta, Pinar Tözün, Anastasia Ailamaki, Andreas Moshovos	SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads.	MICRO	2012	DBLP DOI BibTeX RDF
17	Akbar Sharifi, Emre Kultursay, Mahmut T. Kandemir, Chita R. Das	Addressing End-to-End Memory Access Latency in NoC-Based Multicores.	MICRO	2012	DBLP DOI BibTeX RDF
17	Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides	The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.	MICRO	2012	DBLP DOI BibTeX RDF
17	Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt	Predicting Performance Impact of DVFS for Realistic Memory Systems.	MICRO	2012	DBLP DOI BibTeX RDF
17	Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi	A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch.	MICRO	2012	DBLP DOI BibTeX RDF
17	Rami Sheikh, James Tuck 0001, Eric Rotenberg	Control-Flow Decoupling.	MICRO	2012	DBLP DOI BibTeX RDF
17	Timothy Hayes 0001, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero	Vector Extensions for Decision Support DBMS Acceleration.	MICRO	2012	DBLP DOI BibTeX RDF
17	Ramon Bertran, Alper Buyuktosunoglu, Meeta Sharma Gupta, Marc González 0001, Pradip Bose	Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.	MICRO	2012	DBLP DOI BibTeX RDF
17	Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides	NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.	MICRO	2012	DBLP DOI BibTeX RDF
17	Moinuddin K. Qureshi, Gabriel H. Loh	Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design.	MICRO	2012	DBLP DOI BibTeX RDF
17	Yale N. Patt	HPS Microarchitecture.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
17	Josef Weidendorfer	Intel Core Microarchitecture, x86 Processor Family.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
17	Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu	Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
17	Nan Zhang	Resolving a L2-prefetch-caused parallel nonscaling on Intel Core microarchitecture.	J. Parallel Distributed Comput.	2011	DBLP DOI BibTeX RDF
17	Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
17	Efi Rotem, Alon Naveh, Doron Rajwan, Avinash Ananthakrishnan, Eliezer Weissmann	Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge.	Hot Chips Symposium	2011	DBLP DOI BibTeX RDF
17	Chia-I Chen, Juinn-Dar Huang	Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family.	ISVLSI	2011	DBLP DOI BibTeX RDF
17	Henry Wong, Vaughn Betz, Jonathan Rose	Comparing FPGA vs. custom cmos and the impact on processor microarchitecture.	FPGA	2011	DBLP DOI BibTeX RDF
17	Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic (eds.)	44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011	MICRO	2011	DBLP BibTeX RDF
17	Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer	Abstraction and microarchitecture scaling in early-stage power modeling.	HPCA	2011	DBLP DOI BibTeX RDF
17	David Raymond Lutz	Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add Pipelines.	IEEE Symposium on Computer Arithmetic	2011	DBLP DOI BibTeX RDF
17	Ralf König 0001, Timo Stripf, Jan Heisswolf, Jürgen Becker 0001	A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
17	Ryuichi Takahashi, Yoshiyasu Takefuji	SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project.	MSE	2011	DBLP DOI BibTeX RDF
17	Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang 0003	AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
17	Jingweijia Tan, Nilanjan Goswami, Tao Li 0006, Xin Fu	Analyzing soft-error vulnerability on GPGPU microarchitecture.	IISWC	2011	DBLP DOI BibTeX RDF
17	Yuhao Zhu 0001, Yangdong Deng, Yubei Chen	Hermes: an integrated CPU/GPU microarchitecture for IP routing.	DAC	2011	DBLP DOI BibTeX RDF
17	Ziyad Hanna	A symbolic execution framework for algorithm-level modelling and verification of computer microarchitecture.		2011	RDF
17	Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu	CoreRacer: a practical memory race recorder for multicore x86 TSO processors.	MICRO	2011	DBLP DOI BibTeX RDF
17	Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John	Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.	MICRO	2011	DBLP DOI BibTeX RDF
17	Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt	Improving GPU performance via large warps and two-level warp scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
17	Jesse G. Beu, Michel C. Rosier, Thomas M. Conte	Manager-client pairing: a framework for implementing coherence hierarchies.	MICRO	2011	DBLP DOI BibTeX RDF
17	Yan Pan, John Kim, Gokhan Memik	FeatherWeight: low-cost optical arbitration with QoS support.	MICRO	2011	DBLP DOI BibTeX RDF
17	Marc de Kruijf, Karthikeyan Sankaralingam	Idempotent processor architecture.	MICRO	2011	DBLP DOI BibTeX RDF
17	Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt	Hardware transactional memory for GPU architectures.	MICRO	2011	DBLP DOI BibTeX RDF
17	Jiaqi Zhang, Weiwei Xiong, Yang Liu 0044, Soyeon Park, Yuanyuan Zhou 0001, Zhiqiang Ma	ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer.	MICRO	2011	DBLP DOI BibTeX RDF
17	Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter	Active management of timing guardband to save energy in POWER7.	MICRO	2011	DBLP DOI BibTeX RDF
17	Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh 0001	Architectural support for secure virtualization under a vulnerable hypervisor.	MICRO	2011	DBLP DOI BibTeX RDF
17	Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt	Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.	MICRO	2011	DBLP DOI BibTeX RDF
17	Mitchell Hayenga, Mikko H. Lipasti	The NoX router.	MICRO	2011	DBLP DOI BibTeX RDF
17	Yuanrui Zhang, Wei Ding 0008, Mahmut T. Kandemir, Jun Liu 0008, Ohyoung Jang	A data layout optimization framework for NUCA-based multicores.	MICRO	2011	DBLP DOI BibTeX RDF
17	Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda	Reducing memory interference in multicore systems via application-aware memory channel partitioning.	MICRO	2011	DBLP DOI BibTeX RDF
17	Jing Xin, Russ Joseph	Identifying and predicting timing-critical instructions to boost timing speculation.	MICRO	2011	DBLP DOI BibTeX RDF
17	Qing Guo 0004, Xiaochen Guo, Yuxin Bai, Engin Ipek	A resistive TCAM accelerator for data-intensive computing.	MICRO	2011	DBLP DOI BibTeX RDF
17	Michael Ferdman, Cansu Kaynak, Babak Falsafi	Proactive instruction fetch.	MICRO	2011	DBLP DOI BibTeX RDF
17	Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	SHiP: signature-based hit predictor for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
17	Ritesh Parikh, Valeria Bertacco	Formally enhanced runtime verification to ensure NoC functional correctness.	MICRO	2011	DBLP DOI BibTeX RDF
17	Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger	Preventing PCM banks from seizing too much power.	MICRO	2011	DBLP DOI BibTeX RDF
17	Mark Gebhart, Stephen W. Keckler, William J. Dally	A compile-time managed multi-level register file hierarchy.	MICRO	2011	DBLP DOI BibTeX RDF
17	Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	PACMan: prefetch-aware cache management for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
17	Gabriel H. Loh, Mark D. Hill	Efficiently enabling conventional block sizes for very large die-stacked DRAM caches.	MICRO	2011	DBLP DOI BibTeX RDF
17	Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili	SIMD re-convergence at thread frontiers.	MICRO	2011	DBLP DOI BibTeX RDF
17	Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda	Pack & Cap: adaptive DVFS and thread packing under power caps.	MICRO	2011	DBLP DOI BibTeX RDF
17	Moinuddin K. Qureshi	Pay-As-You-Go: low-overhead hard-error correction for phase change memories.	MICRO	2011	DBLP DOI BibTeX RDF
17	Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti	CRAM: coded registers for amplified multiporting.	MICRO	2011	DBLP DOI BibTeX RDF
17	Zhenyu Sun 0001, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu	Multi retention level STT-RAM cache designs with a dynamic refresh scheme.	MICRO	2011	DBLP DOI BibTeX RDF
17	Gabriel H. Loh	A register-file approach for row buffer caches in die-stacked DRAMs.	MICRO	2011	DBLP DOI BibTeX RDF
17	Sheng Li 0007, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi	System-level integrated server architectures for scale-out datacenters.	MICRO	2011	DBLP DOI BibTeX RDF
17	André Seznec	A new case for the TAGE branch predictor.	MICRO	2011	DBLP DOI BibTeX RDF
17	Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt	Parallel application memory scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
17	Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson	QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.	MICRO	2011	DBLP DOI BibTeX RDF
17	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August	Bundled execution of recurring traces for energy-efficient general purpose processing.	MICRO	2011	DBLP DOI BibTeX RDF
17	Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa	Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations.	MICRO	2011	DBLP DOI BibTeX RDF
17	Christopher Nitta, Matthew K. Farrens, Venkatesh Akella	Resilient microring resonator based photonic networks.	MICRO	2011	DBLP DOI BibTeX RDF
17	Soontae Kim, Jongmin Lee 0002, Jesung Kim, Seokin Hong	Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.	MICRO	2011	DBLP DOI BibTeX RDF
17	George Michelogiannakis, Nan Jiang 0009, Daniel Becker 0003, William J. Dally	Packet chaining: efficient single-cycle allocation for on-chip networks.	MICRO	2011	DBLP DOI BibTeX RDF
17	Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González 0001	Accelerating microprocessor silicon validation by exposing ISA diversity.	MICRO	2011	DBLP DOI BibTeX RDF
17	Gagan Gupta, Gurindar S. Sohi	Dataflow execution of sequential imperative programs on multicore architectures.	MICRO	2011	DBLP DOI BibTeX RDF
17	Konstantinos Aisopos, Li-Shiuan Peh	A systematic methodology to develop resilient cache coherence protocols.	MICRO	2011	DBLP DOI BibTeX RDF
17	Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August	Encore: low-cost, fine-grained transient fault recovery.	MICRO	2011	DBLP DOI BibTeX RDF
17	Ahmed H. Abdel-Gawad, Mithuna Thottethodi	TransCom: transforming stream communication for load balance and efficiency in networks-on-chip.	MICRO	2011	DBLP DOI BibTeX RDF