| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Muhammad Awais 0004, Ashwani Singh, Emmanuel Boutillon, Guido Masera |
A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder.  |
DSD  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tom Van Leeuwen 0002, Rene van Leuken 0001 |
A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ghazaleh Nazarian, Christos Strydis, Georgi Gaydadjiev |
Compatibility Study of Compile-Time Optimizations for Power and Reliability. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Farshad Firouzi, Amir Yazdanbakhsh, Hamed Dorosti, Sied Mehdi Fakhraie |
Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Maistri, Régis Leveugle |
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Roudel, François Berry, Jocelyn Sérot, Laurent Eck |
A New High-Level Methodology for Programming FPGA-Based Smart Camera. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Malek Naoues, Laurent Alaus, Dominique Noguet |
A Common Operator for FFT and Viterbi Algorithms. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt |
A Parallel for Loop Memory Template for a High Level Synthesis Compiler. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan Núñez 0002, Maria J. Avedillo, José M. Quintana |
Evaluation of RTD-CMOS Logic Gates. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík |
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tim Kranich, Mladen Berekovic |
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kees Goossens, Dongrui She, Aleksandar Milutinovic, Anca Mariana Molnos |
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepak Kumar, Pankaj Kumar, Manisha Pattanaik |
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys |
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi 0001, Mehdi Baradaran Tahoori |
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería |
Filtering Directory Lookups in CMPs. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Salehi, Amirali Baniasadi |
Storage-Aware Value Prediction. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar |
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Zdenek Prikryl, Karel Masarík, Tomás Hruska, Adam Husár |
Generated Cycle-Accurate Profiler for C Language. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Son Truong Nguyen, Shigeru Oyanagi |
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonio da Silva 0001, Sebastián Sánchez 0001 |
LEON3 ViP: A Virtual Platform with Fault Injection Capabilities. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maurizio Palesi, Rickard Holsmark, Xiaohang Wang 0001, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania |
An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit |
Adaptive Beamforming Using the Reconfigurable MONTIUM TP. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Somayyeh Koohi, Alireza Shafaei, Shaahin Hessabi |
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid |
Automated Power Characterization for Run-Time Power Emulation of SoC Designs. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | José Luis Risco-Martín, José Manuel Colmenar, David Atienza, José Ignacio Hidalgo |
Simulation of High-Performance Memory Allocators. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nastaran Salehi, Ahmad Khadem Zadeh, Arash Dana |
Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cor Meenderinck, Ben H. H. Juurlink |
A Case for Hardware Task Management Support for the StarSS Programming Model. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana |
Description-Level Optimisation of Synthesisable Asynchronous Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Elias Baaklini, Hassan Sbeity, Smaïl Niar, Nouhad Amaneddine |
H.264 Color Components Video Decoding Parallelization on Multi-core Processors. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Fernando Pescador, Eduardo Juárez Martínez, David Samper Martínez, César Sanz, Mickaël Raulet |
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Hotoleanu, Octavian Cret, Alin Suciu, Tamas Györfi, Lucia Vacariu |
Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Somsubhra Talapatra, Hafizur Rahaman 0001, Samir K. Saha |
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m). |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Igor Lemberski, Petr Fiser |
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker |
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume |
Optimising Self-Timed FPGA Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stanislaw J. Piestrak |
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors |
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Barend van Liempd, Daniel Herrera, Miguel E. Figueroa |
An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yun Jie Wu, Dominique Houzet, Sylvain Huet |
A Programming Model and a NoC-Based Architecture for Streaming Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Antoni Roca 0001, José Flich, Federico Silla, José Duato |
A Latency-Efficient Router Architecture for CMP Systems. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian Wang 0035, Joar Sohl, Olof Kraigher, Dake Liu |
Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrea Marongiu, Paolo Burgio, Luca Benini |
Evaluating OpenMP Support Costs on MPSoCs. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Makoto Sugihara |
Dynamic Control Flow Checking Technique for Reliable Microprocessors. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu |
A Computation and Power Reduction Technique for H.264 Intra Prediction. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsutomu Sasao |
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo |
Adaptive Cache Memories for SMT Processors. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Imtiaz Sajid, Sotirios G. Ziavras, Muhammad Mansoor Ahmed |
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Suárez-Casal, Angel Carro-Lagoa, José Antonio García-Naya, Luis Castedo |
A Multicore SDR Architecture for Reconfigurable WiMAX Downlink. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Saad Mubeen, Shashi Kumar |
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin Wu, Guido Masera |
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Félix Moreno, Ignacio López, Ricardo Sanz |
A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | J. F. Tarillo, Nikolaos Mavrogiannakis, Carlos Arthur Lang Lisbôa, Costas Argyrides, Luigi Carro |
Multiple Bit Error Detection and Correction in Memory. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi He 0008, Ju Ren 0002, Mei Wen, Qianming Yang, Nan Wu 0003, Chunyuan Zhang |
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Rozkovec, Jiri Jenícek, Ondrej Novák |
Application Dependent FPGA Testing Method. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Franco Fummi, Giovanni Perbellini, Davide Quaglia, R. Trenti |
Exploration of Network Alternatives for Middleware-centric Embedded System Design. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina |
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf |
Architectural Vulnerability Factor Estimation with Backwards Analysis. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcus Jeitler, Jakob Lechner |
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, Marco Gerards |
C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sander Stuijk, Marc Geilen, Twan Basten |
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari |
A Multicore Embedded Processor for Fingerprint Recognition. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | George Kornaros, Antonios Motakis |
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Lange, Naim Harb, Haisheng Liu, Smaïl Niar, Rabie Ben Atitallah |
An Improved Automotive Multiple Target Tracking System Design. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai |
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera |
ALOE-Based Flexible LDPC Decoder. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro |
System Level Hardening by Computing with Matrices. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrique Barajas, Diego Mateo, José Luis González 0001 |
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo |
A Modular Peripheral to Support Self-Reconfiguration in SoCs. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Adolfo Recio, Peter M. Athanas |
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Straka, Jan Kastil, Zdenek Kotásek |
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Toktam Taghavi, Andy D. Pimentel |
Visualization of Multi-objective Design Space Exploration for Embedded Systems. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Zhang 0002, Hans G. Kerkhoff, Bart Vermeulen |
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Cao, Albert Nymeyer |
A Markov Model for Low-Power High-Fidelity Design-Space Exploration. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Claas Cornelius, Philipp Gorski, Stephan Kubisch, Dirk Timmermann |
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas |
Path-Delay Fault Testing in Embedded Content Addressable Memories. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Paris Kitsos, Nicolas Sklavos 0001, Athanassios N. Skodras |
Low Power FPGA Implementations of 256-bit Luffa Hash Function. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer |
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Felipe Lavratti, Alex R. Pinto, Letícia Maria Veiras Bolzani, Fabian Vargas 0001, Carlos Barros Montez, Fernando Hernandez, Edmundo Gatti, C. Silva |
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ye Gao, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi |
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Balach, Ondrej Novák |
Reconfigurable Fault-Tolerant System Sychronization. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lara G. Villanueva, Gustavo Marrero Callicó, Félix Tobajas, Sebastián López, Valentin de Armas, José Francisco López, Roberto Sarmiento |
Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Miguel Lino Silva, João Canas Ferreira |
Creation of Partial FPGA Configurations at Run-Time. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vrishali Vijay Nimbalkar, Kuruvilla Varghese |
In-channel Flow Control Scheme for Network-on-Chip. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alice M. Tokarnia, Marina Tachibana |
Design of Trace-Based Split Array Caches for Embedded Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shohreh Sharif Mansouri, Elena Dubrova |
An Improved Hardware Implementation of the Grain Stream Cipher. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ricardo Severino, Manish Batsa, Mário Alves, Anis Koubaa |
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie |
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhufei Chu, Yinshui Xia, William N. N. Hung, Lun-Yao Wang, Xiaoyu Song |
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler |
RobuCheck: A Robustness Checker for Digital Circuits. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Patooghy, Hamed Tabkhi, Seyed Ghassem Miremadi |
An Efficient Method to Reliable Data Transmission in Network-on-Chips. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Francisco Sánchez, Juan Carlos López 0001 |
Persistence Management Model for Dynamically Reconfigurable Hardware. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Majd Ghazi Batarseh, Ehab Shobaki, Xiang Fang, Haibing Hu, Issa Batarseh |
New Digital Control Technique for Improving Transient Response in DC - DC Converters. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Richard Ruzicka |
Gracefully Degrading Circuit Controllers Based on Polytronics. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Bakalis, Haridimos T. Vergos |
Area-Efficient Multi-moduli Squarers for RNS. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiri Balcarek, Petr Fiser, Jan Schmidt |
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tingcong Ye, Dilip P. Vasudevan, Jiaoyan Chen, Emanuel M. Popovici, Michel P. Schellekens |
Static Average Case Power Estimation Technique for Block Ciphers. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Reichenbach, Alexander Wold |
Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications? |
DSD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa |
Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations. |
DSD |
2010 |
DBLP DOI BibTeX RDF |
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