Search results for "DSD"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso	A Formal Condition to Stop an Incremental Automatic Functional Diagnosis.	DSD	2010	DBLP DOI BibTeX RDF
1	Marta Stepniewska, Adam Luczak, Jakub Siast	Network-on-Multi-Chip (NoMC) for Multi-FPGA Multimedia Systems.	DSD	2010	DBLP DOI BibTeX RDF
1	Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel	The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption.	DSD	2010	DBLP DOI BibTeX RDF
1	Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni	Re-NUCA: Boosting CMP Performance Through Block Replication.	DSD	2010	DBLP DOI BibTeX RDF
1	Andrea Castagnetti, Cécile Belleudy, Sébastien Bilavarn, Michel Auguin	Power Consumption Modeling for DVFS Exploitation.	DSD	2010	DBLP DOI BibTeX RDF
1	Ozgur Tasdizen, Ilker Hamzaoglu	Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation.	DSD	2010	DBLP DOI BibTeX RDF
1	Allen Chen, Ryan Hoppal, Tom Chen 0001	On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications.	DSD	2010	DBLP DOI BibTeX RDF
1	Levent Aksoy, Eduardo Costa 0001, Paulo F. Flores, José Monteiro 0001	Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications.	DSD	2010	DBLP DOI BibTeX RDF
1	René Kothe, Heinrich Theodor Vierhaus	Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures.	DSD	2010	DBLP DOI BibTeX RDF
1	Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser	Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis.	DSD	2010	DBLP DOI BibTeX RDF
1	Subayal Khan, Kari Tiensyrjä, Jari Nurmi	Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile.	DSD	2010	DBLP DOI BibTeX RDF
1	Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit	An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits.	DSD	2010	DBLP DOI BibTeX RDF
1	Tim Todman, Qiang Liu 0011, Wayne Luk, George A. Constantinides	Customizable Composition and Parameterization of Hardware Design Transformations.	DSD	2010	DBLP DOI BibTeX RDF
1	Masaru Takesue	A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism.	DSD	2010	DBLP DOI BibTeX RDF
1	Florent Berthelot, François Charot, Charles Wagner, Christophe Wolinski	Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation.	DSD	2010	DBLP DOI BibTeX RDF
1	Sebastián López (eds.)	13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France	DSD	2010	DBLP BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A Packet Classifier Using a Parallel Branching Program Machine.	DSD	2010	DBLP DOI BibTeX RDF
1	Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera	High Performance Image Processing on a Massively Parallel Processor Array.	DSD	2009	DBLP DOI BibTeX RDF
1	Luis A. Tarazona, Doug A. Edwards, Luis A. Plana	A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor.	DSD	2009	DBLP DOI BibTeX RDF
1	Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler	Robustness Check for Multiple Faults Using Formal Techniques.	DSD	2009	DBLP DOI BibTeX RDF
1	Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris	Compilation Technique for Loop Overhead Minimization.	DSD	2009	DBLP DOI BibTeX RDF
1	Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit	A Concept for Logic Self Repair.	DSD	2009	DBLP DOI BibTeX RDF
1	Adam Pawlak, Piotr Penkala, Pawel Fras, Wojciech Sakowski, Günter Grau, Szymon Grzybek, Alexander Stanitzki	Distributed Collaborative Design of a Mixed-Signal IP Component.	DSD	2009	DBLP DOI BibTeX RDF
1	Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas	An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.	DSD	2009	DBLP DOI BibTeX RDF
1	Sandro Penolazzi, Luca Bolognino, Ahmed Hemani	Energy and Performance Model of a SPARC Leon3 Processor.	DSD	2009	DBLP DOI BibTeX RDF
1	Giovanni Danese, Mauro Giachero, Francesco Leporati, Giulia Matrone, Nelson Nazzicari	An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm.	DSD	2009	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Kostin, Jaan Raik	Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems.	DSD	2009	DBLP DOI BibTeX RDF
1	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.	DSD	2009	DBLP DOI BibTeX RDF
1	Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen	Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks.	DSD	2009	DBLP DOI BibTeX RDF
1	Evangelos Vassalos, Dimitris Bakalis	Combined SD-RNS Constant Multiplication.	DSD	2009	DBLP DOI BibTeX RDF
1	Ioannis Kouretas, Vassilis Paliouras	Variation-tolerant Design Using Residue Number System.	DSD	2009	DBLP DOI BibTeX RDF
1	Damien Hedde, Pierre-Henri Horrein, Frédéric Pétrot, Robin Rolland, Franck Rousseau	A MPSoC Prototyping Platform for Flexible Radio Applications.	DSD	2009	DBLP DOI BibTeX RDF
1	Jan Schmidt, Petr Fiser	The Case for a Balanced Decomposition Process.	DSD	2009	DBLP DOI BibTeX RDF
1	Ahmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis, Miguel Corbalan Miranda, Bart Dierickx, Maarten Kuijk	A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning.	DSD	2009	DBLP DOI BibTeX RDF
1	Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane	FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash.	DSD	2009	DBLP DOI BibTeX RDF
1	Anca Mariana Molnos, Kees Goossens	Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors.	DSD	2009	DBLP DOI BibTeX RDF
1	Zheng Shen, Hu He 0001, Yihe Sun	Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism.	DSD	2009	DBLP DOI BibTeX RDF
1	Jaroslav Borecký, Pavel Kubalík, Hana Kubátová	Reliable Railway Station System Based on Regular Structure Implemented in FPGA.	DSD	2009	DBLP DOI BibTeX RDF
1	Li Tong, Zhonghai Lu, Hua Zhang	Exploration of Slot Allocation for On-Chip TDM Virtual Circuits.	DSD	2009	DBLP DOI BibTeX RDF
1	Petr Mikusek, Václav Dvorák	Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization.	DSD	2009	DBLP DOI BibTeX RDF
1	Marco Gerards, Jan Kuper, André B. J. Kokkeler, Bert Molenkamp	Streaming Reduction Circuit.	DSD	2009	DBLP DOI BibTeX RDF
1	Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee	Survey of Test Data Compression Technique Emphasizing Code Based Schemes.	DSD	2009	DBLP DOI BibTeX RDF
1	Franco Fummi, Davide Quaglia, Francesco Stefanni	Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems.	DSD	2009	DBLP DOI BibTeX RDF
1	Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales	An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures.	DSD	2009	DBLP DOI BibTeX RDF
1	Julien Lallet, Sébastien Pillement, Olivier Sentieys	xMAML: A Modeling Language for Dynamically Reconfigurable Architectures.	DSD	2009	DBLP DOI BibTeX RDF
1	Victor Silva 0001, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto	Run-Time Reconfigurable Array Using Magnetic RAM.	DSD	2009	DBLP DOI BibTeX RDF
1	Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick	An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication.	DSD	2009	DBLP DOI BibTeX RDF
1	Amin El Mrabti, Hamed Sheibanyrad, Frédéric Rousseau 0001, Frédéric Pétrot, Romain Lemaire, Jérôme Martin	Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation.	DSD	2009	DBLP DOI BibTeX RDF
1	Petr Fiser, David Toman 0002	A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms.	DSD	2009	DBLP DOI BibTeX RDF
1	Andreas Lankes, Thomas Wild, Andreas Herkersdorf	Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources.	DSD	2009	DBLP DOI BibTeX RDF
1	Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm.	DSD	2009	DBLP DOI BibTeX RDF
1	David Guzmán, Manuel Prieto 0003, Daniel Garcia, Victor Ruiz, Javier Almena, Sebastián Sánchez-Prieto, Daniel Meziat	High Reliable Remote Terminal Unit for Space Applications.	DSD	2009	DBLP DOI BibTeX RDF
1	Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser	Model-Driven Design of Embedded Multimedia Applications on SoCs.	DSD	2009	DBLP DOI BibTeX RDF
1	Raj Kumar Nagpal, Rakesh Malik, Jai Narayan Tripathi	Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links.	DSD	2009	DBLP DOI BibTeX RDF
1	Fabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Ktenas, Yvain Thonnart	An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application.	DSD	2009	DBLP DOI BibTeX RDF
1	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi, Javier Sosa, Héctor Navarro	Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications.	DSD	2009	DBLP DOI BibTeX RDF
1	Nikos Petrellis, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas	Calibration Method for a CMOS 0.06mm2 150MS/s 8-bit ADC.	DSD	2009	DBLP DOI BibTeX RDF
1	Apostolos P. Fournaris, Odysseas G. Koufopavlou	One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm.	DSD	2009	DBLP DOI BibTeX RDF
1	Arturo Diaz-Perez, Mario Alberto Garcia Martinez	FPGA Accelerator for RNA Secondary Structure Prediction.	DSD	2009	DBLP DOI BibTeX RDF
1	Michael Birner, Thomas Handl	ARROW - A Generic Hardware Fault Injection Tool for NoCs.	DSD	2009	DBLP DOI BibTeX RDF
1	Oana Boncalo, Alexandru Amaricai	Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation.	DSD	2009	DBLP DOI BibTeX RDF
1	Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf	An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs.	DSD	2009	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, François Charot	Architecture-Driven Synthesis of Reconfigurable Cells.	DSD	2009	DBLP DOI BibTeX RDF
1	Anna Bernasconi 0001, Valentina Ciriani, Gabriella Trucco, Tiziano Villa	Logic Minimization and Testability of 2SPP-P-Circuits.	DSD	2009	DBLP DOI BibTeX RDF
1	Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi	A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling.	DSD	2009	DBLP DOI BibTeX RDF
1	Zhiyuan He 0002, Zebo Peng, Petru Eles	Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment.	DSD	2009	DBLP DOI BibTeX RDF
1	José Carlos Alves, Nuno Alexandre Cruz	An FPGA-Based Embedded System for a Sailing Robot.	DSD	2009	DBLP DOI BibTeX RDF
1	Thomas Tsiolakis, Nikos Konofaos, George Alexiou	Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder.	DSD	2009	DBLP DOI BibTeX RDF
1	Kees Goossens, Lotfi Mhamdi, Iria Varela Senin	Internet-Router Buffered Crossbars Based on Networks on Chip.	DSD	2009	DBLP DOI BibTeX RDF
1	Feng Liu 0029, Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed, Gang Chen 0004, Xiaoyu Song, QingPing Tan	A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC.	DSD	2009	DBLP DOI BibTeX RDF
1	Milan Nenad Simic, Randeep Singh, Louis Doukas, Aliakbar Akbarzadeh	Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds.	DSD	2009	DBLP DOI BibTeX RDF
1	Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus	Reliability Estimation Process.	DSD	2009	DBLP DOI BibTeX RDF
1	Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi	High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output.	DSD	2009	DBLP DOI BibTeX RDF
1	Andrea Ricci, Ilaria De Munari, Paolo Ciampolini	Performance-Effective Compaction of Standard-Cell Libraries for Digital Design.	DSD	2009	DBLP DOI BibTeX RDF
1	Mengxiao Liu, Weixing Ji, Jiaxin Li, Xing Pu	Storage Architecture for an On-chip Multi-core Processor.	DSD	2009	DBLP DOI BibTeX RDF
1	Eric Senn, David Monnereau, André Rossi, Nathalie Julien	Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors.	DSD	2009	DBLP DOI BibTeX RDF
1	Martin Straka, Zdenek Kotásek	High Availability Fault Tolerant Architectures Implemented into FPGAs.	DSD	2009	DBLP DOI BibTeX RDF
1	Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania	Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip.	DSD	2009	DBLP DOI BibTeX RDF
1	Antonio Núñez, Pedro P. Carballo (eds.)	12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece	DSD	2009	DBLP BibTeX RDF
1	Dominique Nussbaum, Karim Khalfallah, Christophe Moy, Amor Nafkha, Pierre Leray, Julien Delorme, Jacques Palicot, Jérôme Martin, Fabien Clermidy, Bertrand Mercier, Renaud Pacalet	Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques.	DSD	2009	DBLP DOI BibTeX RDF
1	Robert Czerwinski, Dariusz Kania	CPLD-oriented Synthesis of Finite State Machines.	DSD	2009	DBLP DOI BibTeX RDF
1	Carlo Brandolese, William Fornaciari	A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes.	DSD	2009	DBLP DOI BibTeX RDF
1	Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu	A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation.	DSD	2009	DBLP DOI BibTeX RDF
1	Meysam Taassori, Shaahin Hessabi	Low Power Encoding in NoCs Based on Coupling Transition Avoidance.	DSD	2009	DBLP DOI BibTeX RDF
1	Antonio da Silva 0001, Sebastián Sánchez 0001	Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models.	DSD	2009	DBLP DOI BibTeX RDF
1	Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França	GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids.	DSD	2009	DBLP DOI BibTeX RDF
1	Alexandru Amaricai, Oana Boncalo	Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation.	DSD	2009	DBLP DOI BibTeX RDF
1	D. Michael Miller, Robert Wille, Gerhard W. Dueck	Synthesizing Reversible Circuits for Irreversible Functions.	DSD	2009	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura	The Parallel Sieve Method for a Virus Scanning Engine.	DSD	2009	DBLP DOI BibTeX RDF
1	Ming-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, Yu-Xin Bai	Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip.	DSD	2009	DBLP DOI BibTeX RDF
1	Amit Kumar Singh 0002, Wu Jigang, Alok Prakash, Thambipillai Srikanthan	Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms.	DSD	2009	DBLP DOI BibTeX RDF
1	Peter Tummeltshammer, Andreas Steininger	On the Risk of Fault Coupling over the Chip Substrate.	DSD	2009	DBLP DOI BibTeX RDF
1	Yoshiyasu Ogasawara, Hironori Nakajo	An Effective Replacement Strategy of Cache Memory for an SMT Processor.	DSD	2009	DBLP DOI BibTeX RDF
1	Daniel Piso Fernandez, Javier D. Bruguera	Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation.	DSD	2009	DBLP DOI BibTeX RDF
1	Xiao Zhang 0002, Hans G. Kerkhoff	Design of a Highly Dependable Beamforming Chip.	DSD	2009	DBLP DOI BibTeX RDF
1	Ayse K. Coskun, Andrew B. Kahng, Tajana Simunic Rosing	Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures.	DSD	2009	DBLP DOI BibTeX RDF
1	Hamid Reza Ahmadi, Ali Afzali-Kusha	Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm.	DSD	2009	DBLP DOI BibTeX RDF
1	Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi	Improving Latency of Quantum Circuits by Gate Exchanging.	DSD	2009	DBLP DOI BibTeX RDF
1	Werner Friesenbichler, Andreas Steininger	Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic.	DSD	2009	DBLP DOI BibTeX RDF
1	Benny Akesson, Andreas Hansson 0001, Kees Goossens	Composable Resource Sharing Based on Latency-Rate Servers.	DSD	2009	DBLP DOI BibTeX RDF

Publications at "DSD"( http://dblp.L3S.de/Venues/DSD )