Search results for "radix-2"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Adnan Suleiman, Hani H. Saleh, Adel Hussein, David Akopian	A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications.	ICCD	2008	DBLP DOI BibTeX RDF
14	Xue Wen, Mark Sandler 0001	Calculation of radix-2 discrete multiresolution Fourier transform.	Signal Process.	2007	DBLP DOI BibTeX RDF
14	Abdurazzag Sulaiman Almiladi, M. K. Ibrahim, M. Al Akidi, A. Aggoun	High-performance scalable bidirectional mixed radix-2 n serial-serial multipliers.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
14	Omar Nibouche, Said Boussakta, Michael Darnell	A New Architecture For Radix-2 New Mersenne Number Transform.	ICC	2006	DBLP DOI BibTeX RDF
14	Philcho Philipov, Vladimir Lazarov, Zahari Zlatev, M. Ivanova	A Parallel Architecture for Radix-2 Fast Fourier Transform.	John Vincent Atanasoff Symposium	2006	DBLP DOI BibTeX RDF	Highperformance computer architectures, Parallel Fast Fourier Transform
14	Gin-Der Wu, Ying Lei	Low power pipelined radix-2 FFT processor for speech recognition.	SoSE	2006	DBLP DOI BibTeX RDF
14	Anup K. C, Ajay Kumar Bangla	A new efficient implementation of TDAC synthesis filterbank based on Radix-2 FFT.	EUSIPCO	2006	DBLP BibTeX RDF
14	Jung-Yeol Oh, Myoung Seob Lim	New Radix-2 to the 4th Power Pipeline FFT Processor.	IEICE Trans. Electron.	2005	DBLP DOI BibTeX RDF
14	Saad Bouguezel, M. Omair Ahmad, M. N. Shanmukha Swamy	A note on "Split vector-radix-2/8 2-D Fast Fourier Transform".	IEEE Signal Process. Lett.	2005	DBLP DOI BibTeX RDF
14	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An efficient multidimensional decimation-in-frequency FHT algorithm based on the radix-2/4 approach.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Soo-Chang Pei, Wei-Yu Chen	Split vector-radix-2/8 2-D fast Fourier transform.	IEEE Signal Process. Lett.	2004	DBLP DOI BibTeX RDF
14	Babak Nejati, Omid Shoaei	Systematic design of the pipelined analog-to-digital converter with radix<2.	Microelectron. J.	2004	DBLP DOI BibTeX RDF
14	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A new radix-2/8 FFT algorithm for length-q×2m DFTs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
14	Narayanam Ranganadh, Parimal Patel, Artyom M. Grigoryan	Implementation of the DFT Using Radix-2 and Paired Transform Algorithms.	CAINE	2004	DBLP BibTeX RDF
14	Babak Nejati, Omid Shoaei	A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter.	ISCAS (1)	2004	DBLP BibTeX RDF
14	Dae Won Kim, Jun Rim Choi	Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder.	Integr.	2003	DBLP DOI BibTeX RDF
14	Paul Rodríguez V.	A radix-2 FFT algorithm for Modern Single Instruction Multiple Data (SIMD) architectures.	ICASSP	2002	DBLP DOI BibTeX RDF
14	Paul Rodríguez	Radix-2 multi-dimensional transposition-free FFT algorithm for Modern Single Instruction Multiple Data (SIMD) architectures.	EUSIPCO	2002	DBLP BibTeX RDF
14	Said Boussakta, Osama Alshibami, M. Y. Aziz	Radix-2 × 2 × 2 algorithm for the 3-D discrete Hartley transform.	IEEE Trans. Signal Process.	2001	DBLP DOI BibTeX RDF
14	Alexandre F. Tenca, Syed Ubaid Hussaini	A Design of Radix-2 On-line Division Using LSA Organization.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
14	T. Sansaloni, A. Perez-Pascual, Javier Valls	Distributed arithmetic radix-2 butterflies for FPGA.	ICECS	2001	DBLP DOI BibTeX RDF
14	B. R. Sekhar, K. M. M. Prabhu	Radix-2 decimation-in-frequency algorithm for the computation of the real-valued FFT.	IEEE Trans. Signal Process.	1999	DBLP DOI BibTeX RDF
14	Jen-Shiun Chiang, Hung-Da Chung, Ming-Hsou Tsai	A radix-2 general division algorithm with carry-free scheme and the divider implementation.	ICECS	1999	DBLP DOI BibTeX RDF
14	Stefan Goedecker	Fast Radix 2, 3, 4, and 5 Kernels for Fast Fourier Transformations on Computers with Overlapping Multiply-Add Instructions.	SIAM J. Sci. Comput.	1997	DBLP DOI BibTeX RDF
14	Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo	Radix 2 Division with Over-Redundant Quotient Selection.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF
14	K. M. M. Prabhu, Nagesh Anupindi, R. Shanmuga Sundaram	Generalized pruning at the input of radix-2 DIF FHT algorithm.	Signal Process.	1996	DBLP DOI BibTeX RDF
14	Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata	Unified Mixed Radix 2-4 Redundant CORDIC Processor.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
14	Paolo Montuschi, Luigi Ciminiera	A Remark on "Reducing Iteration Time when Result Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders".	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
14	Jean-Claude Bajard, Jean Duprat, Sylvanus Kla, Jean-Michel Muller	Some Operators for On-Line Radix-2 Computations.	J. Parallel Distributed Comput.	1994	DBLP DOI BibTeX RDF
14	Kyung-Wook Shin, Heung-Woo Jeon, Yong-Seum Kang	An Efficient VLSI Implementation of Vector-Radix 2-D DCT using Mesh-Connected 2-D Array.	ISCAS	1994	DBLP DOI BibTeX RDF
14	Paolo Montuschi, Luigi Ciminiera	Radix-2 Division with Quotient Digit Prediction without Prescaling.	HICSS (1)	1994	DBLP BibTeX RDF
14	Paolo Montuschi, Luigi Ciminiera	Reducing Iteration Time When Result Digit is Zero for Radix 2 SRT Division and Square Root with Redundant Remainders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF
14	Paolo Montuschi, Luigi Ciminiera	Simple radix 2 division and square root with skipping of some addition steps.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
14	S. Lennart Johnsson, Robert L. Krawitz, Roger Frye, Douglas MacDonald	A radix-2 FFT on connection machine.	SC	1989	DBLP DOI BibTeX RDF
14	David T. Harper III, Darel A. Linebarger	Storage Schemes for Efficient Computation of a Radix 2 FFT in a Machine with Parallel Memories.	ICPP (1)	1988	DBLP BibTeX RDF
14	Howard W. Johnson, C. Sidney Burrus	An in-order, in-place radix-2 FFT.	ICASSP	1984	DBLP DOI BibTeX RDF
14	Francis Castanie, D. Wan	Application of the random reference quantization principle to radix-2 FFT computation.	ICASSP	1984	DBLP DOI BibTeX RDF
14	Hitohisa Asai, C. K. Cheng	Speeding Up an Overrelaxation Method of Division in Radix-2^n Machine.	Commun. ACM	1983	DBLP DOI BibTeX RDF
14	Chris R. Jesshope	The Implementation of Fast Radix 2 Transforms on Array Processors.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF
14	Shalhav Zohar	A/D Conversion for Radix (-2).	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
9	Veera Papirla, Aarul Jain, Chaitali Chakrabarti	Low power robust signal processing.	ISLPED	2009	DBLP DOI BibTeX RDF	algorithmic noise tolerance, redundant binary arithmetic, soft DSP
9	Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien	Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Wei-Hsin Chang, Truong Q. Nguyen	On the Fixed-Point Accuracy Analysis of FFT Algorithms.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
9	Tiziano Bianchi, Alessandro Piva, Mauro Barni	Implementing the discrete Fourier transform in the encrypted domain.	ICASSP	2008	DBLP DOI BibTeX RDF
9	Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu	High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.	ISMVL	2008	DBLP DOI BibTeX RDF	Verilog-AMS, Static timing analysis, Look-up table
9	Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li	A novel VLSI iterative divider architecture for fast quotient generation.	ISCAS	2008	DBLP DOI BibTeX RDF
9	Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin	Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
9	In-Cheol Park, WonHee Son, Ji-Hoon Kim	Twiddle factor transformation for pipelined FFT processing.	ICCD	2007	DBLP DOI BibTeX RDF
9	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
9	Akira Mochizuki, Takahiro Hanyu	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
9	Jeesung Lee, Hanho Lee, Sang-in Cho, Sangsung Choi	A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Andreas Persson, Lars Bengtsson	Reverse conversion architectures for signed-digit residue number systems.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Pedro Henrique Cox, Aparecido Augusto de Carvalho	FPGA Discrete Wavelet Transform Encoder/Decoder Implementation.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
9	Majid Khabbazian, T. Aaron Gulliver, Vijay K. Bhargava	A New Minimal Average Weight Representation for Left-to-Right Point Multiplication Methods.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Minimum-weight representation, left-to-right recoding, elliptic curve cryptosystems, efficient implementation, point multiplication
9	Miriam Primbs	Worst-case error analysis of lifting-based fast DCT-algorithms.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
9	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	redundant adders, digit sets, digit encodings, multiplier trees
9	Pavan Adharapurapu, Milos D. Ercegovac	A Linear-System Operator Based Scheme for Evaluation of Multinomials.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
9	Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi	A Hardware Algorithm for Integer Division.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
9	Cuixiang Zhong, Guo-qiang Han, Minghe Huang	Some New Parallel Fast Fourier Transform Algorithms.	PDCAT	2005	DBLP DOI BibTeX RDF
9	Jarmo Takala, Konsta Punkka	Scalable FFT Processors and Pipelined Butterfly Units.	SAMOS	2004	DBLP DOI BibTeX RDF
9	Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo	Power Aware Dividers in FPGA.	PATMOS	2004	DBLP DOI BibTeX RDF
9	Roberto Maria Avanzi	A Note on the Signed Sliding Window Integer Recoding and a Left-to-Right Analogue.	Selected Areas in Cryptography	2004	DBLP DOI BibTeX RDF
9	Haque Mohammad Munirul, Michitaka Kameyama	Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.	ISMVL	2004	DBLP DOI BibTeX RDF
9	M. M. Campello de Souza, Hélio M. de Oliveira, Ricardo M. Campello de Souza, M. M. Vasconcelos	The Discrete Cosine Transform over Prime Finite Fields.	ICT	2004	DBLP DOI BibTeX RDF
9	Justin Hensley, Anselmo Lastra, Montek Singh	An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.	ICCD	2004	DBLP DOI BibTeX RDF
9	Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen	A power-aware IP core generator for the one-dimensional discrete Fourier transform.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
9	Alex Fit-Florea, David W. Matula	A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k.	ASAP	2004	DBLP DOI BibTeX RDF
9	Y. Ibrahim, Graham A. Jullien, William C. Miller	Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks.	IWSOC	2004	DBLP DOI BibTeX RDF
9	Woo-Suk Ko, Joon-Seok Kim 0002, Young-Cheol Park, Tai-Ho Koh, Dae Hee Youn	An efficient DMT modem for the G.LITE ADSL transceiver.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
9	Álvaro Vázquez, Elisardo Antelo	Implementation of the Exponential Function in a Floating-Point Unit.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	exponential function, computer arithmetic, floating-point unit, transcendental functions
9	Marcelo E. Kaihara, Naofumi Takagi	A VLSI Algorithm for Modular Multiplication/Division.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
9	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Dynamic Source-Coupled Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
9	Ciaran McIvor, Máire McLoone, John V. McCanny	A high-speed, low latency RSA decryption silicon core.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
9	Chao-Kai Chang, Chung-Ping Hung, Sau-Gee Chen	An efficient memory-based FFT architecture.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
9	Chuen-Yau Chen, Wen-Chih Liu	Architecture for CORDIC algorithm realization without ROM lookup tables.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
9	Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria	A new memory reference reduction method for FFT implementation on DSP.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
9	Amir Hosein Kamalizad, Chengzhi Pan, Nader Bagherzadeh	Fast Parallel FFT on a Reconfigurable Computation Platform.	SBAC-PAD	2003	DBLP DOI BibTeX RDF
9	Shen-Yi Lin, Chih-Shen Chen, Li Liu, Chua-Huang Huang	Tensor Product Formulation for Hilbert Space-Filling Curves.	ICPP	2003	DBLP DOI BibTeX RDF
9	Amar Aggoun, A. Farwan, M. K. Ibrahim	A radix-2n vector inner product.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
9	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
9	Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall	Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.	ASAP	2002	DBLP DOI BibTeX RDF
9	Chin-Liang Wang, Ching-Hsien Chang	A new memory-based FFT processor for VDSL transceivers.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
9	Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi	A compatible DCT/IDCT architecture using hardwired distributed arithmetic.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
9	Shugang Wei, Kensuke Shimizu	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.	DFT	2001	DBLP DOI BibTeX RDF	residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS)
9	Shugang Wei, Kensuke Shimizu	Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
9	Shen-Fu Hsiao, Jen-Yin Chen	Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
9	Ding-Ming Kwai, Behrooz Parhami	FFT computation with linear processor arrays using a data-driven control scheme.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
9	Vassilliy Tchoumatchenko, Tania Vassileva, P. Gurov	An FPGA-Based Square-Root Co-Processor.	EUROMICRO	1996	DBLP DOI BibTeX RDF
9	Lori Lucke, Chaitali Chakrabarti	A digit-serial architecture for gray-scale morphological filtering.	IEEE Trans. Image Process.	1995	DBLP DOI BibTeX RDF
9	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
9	Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski	A chip set for pipeline and parallel pipeline FFT architectures.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
9	Marianne E. Louie, Milos D. Ercegovac	Implementing division with field programmable gate arrays.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
9	Emilio L. Zapata, Francisco Argüello	A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	fast Hartley transform, VLSI constant geometryarchitecture, parallel calculation, constant geometry algorithm, perfect unshuffle permutation, processormemory, systolic data flow, multiplexing operations, hardwired control, parallel algorithms, VLSI, parallel architecture, parallel architectures, fast Fourier transform, fast Fourier transforms, butterflies, FIFO queues, application-specific architecture, computationalcomplexity
9	Xiaoping Huang, Belle W. Y. Wei, Honglu Chen, Yuhai H. Mao	High-performance VLSI multiplier with a new redundant binary coding.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
9	Paul K.-G. Tu, Milos D. Ercegovac	Gate array implementation of on-line algorithms for floating-point operations.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
9	Abdelhakim Safir, Bertrand Y. Zavidovique	Towards a global solution to high level synthesis problems.	EURO-DAC	1990	DBLP DOI BibTeX RDF