| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa |
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters.  |
ARC  |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Gökhan Akgün, Lester Kalms, Diana Göhringer |
Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Habib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer |
Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani, Dmitriy Fedorov |
StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk |
Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Bacchus, Robert J. Stewart 0001, Ekaterina Komendantskaya |
Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, Smaïl Niar |
Cross-layer CNN Approximations for Hardware Implementation. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Fernando Rincón, Jesús Barba, Hayden Kwok-Hay So, Pedro C. Diniz, Julián Caba (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed]. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Leonardo Suriano, David Lima, Eduardo de la Torre |
Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto |
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Zakarya Guettatfi, Paul Kaufmann, Marco Platzner |
Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Changdao Du, Iman Firmansyah, Yoshiki Yamaguchi |
FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki |
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashish Misra, Volodymyr V. Kindratenko |
HLS-Based Acceleration Framework for Deep Convolutional Neural Networks. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Duc Tri Nguyen, Viet Ba Dang, Kris Gaj |
High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | George Charitopoulos, Dionisios N. Pnevmatikatos |
A CGRA Definition Framework for Dataflow Applications. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Riadh Ben Abdelhamid, Yoshiki Yamaguchi |
A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi |
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa |
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Gökhan Akgün, Habib ul Hasan Khan, Marawan Azmy Hebaish, Mahmoud Ahmed Elshimy, Mohamed A. Abd El Ghany, Diana Göhringer |
SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification. |
ARC |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis Wolf 0001, Tajas Ruschke, Christian Hochberger, Andreas Engel 0003, Andreas Koch 0001 |
UltraSynth: Integration of a CGRA into a Control Engineering Environment. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker 0001 |
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Günter Knittel |
A Novel Encoder for TDCs. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Qian Zhao 0001, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida |
A Resource Reduced Application-Specific FPGA Switch. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Zheming Jin, Hal Finkel |
Evaluating LULESH Kernels on OpenCL FPGA. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Leonard Masing, Fabian Lesniak, Jürgen Becker 0001 |
Hybrid Prototyping for Manycore Design and Validation. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis G. Mousouliotis, Loukas P. Petrou |
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner |
Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Christian Hochberger, Brent Nelson, Andreas Koch 0001, Roger F. Woods, Pedro C. Diniz (eds.) |
Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis |
Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk |
Optimizing CNN-Based Hyperspectral Image Classification on FPGAs. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | João Paulo C. de Lima, Paulo C. Santos 0001, Rafael Fao de Moura, Marco A. Z. Alves, Antonio C. S. Beck, Luigi Carro |
Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lester Kalms, Ariel Podlubne, Diana Göhringer |
HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Piotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka, Tomasz Kryjak |
Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Konstantinos Boikos, Christos-Savvas Bouganis |
A Scalable FPGA-Based Architecture for Depth Estimation in SLAM. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ludovica Bozzoli, Luca Sterpone |
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ana Gonçalves, Tiago Peres, Mário P. Véstias |
Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Korinth, Jaco A. Hofmann, Carsten Heinz, Andreas Koch 0001 |
The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker 0001 |
Secure Local Configuration of Intellectual Property Without a Trusted Third Party. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Johanna Rohde, Lukas Johannes Jung, Christian Hochberger |
Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tiago Peres, Ana Gonçalves, Mário P. Véstias |
Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto |
Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars |
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Masayuki Shimoda, Youki Sada, Hiroki Nakahara |
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | André Werner 0001, Florian Fricke, Keyvan Shahin, Florian Werner 0002, Michael Hübner 0001 |
Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler |
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno da Silva 0001, An Braeken, Abdellah Touhafi |
Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Afonso Canas Ferreira, João M. P. Cardoso |
Graph-Based Code Restructuring Targeting HLS for FPGAs. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Brent E. Nelson |
Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape. |
ARC |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung |
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Littlewood, Shahnam Mirzaei, Krishna Murthy Kattiyan Ramamoorthy |
Reconfigurable IP-Based Spectral Interference Canceller. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner 0001, Fynn Schwiegelshohn, Diana Goehringer, Maria Dagioglou, Georgios Stavrinos, Stasinos Konstantopoulos, Vangelis Karkaletsis |
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart 0001, Greg Michaelson |
Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Augusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker 0001 |
Control Flow Analysis for Embedded Multi-core Hybrid Systems. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalindu Herath, Alok Prakash, Thambipillai Srikanthan |
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Tzanis, Grigorios Proiskos, Michael K. Birbas, Alexios N. Birbas |
FPGA-Assisted Distribution Grid Simulator. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sikandar Khan, Kyprianos Papadimitriou, Giorgio C. Buttazzo, Kostas Kalaitzakis |
A Reconfigurable PID Controller. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung |
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Masahiro Fukuda, Yasushi Inoguchi |
FPGA-Based Parallel Pattern Matching. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Björn Liebig, Julian Oppermann, Oliver Sinnen, Andreas Koch 0001 |
Improved High-Level Synthesis for Complex CellML Models. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio |
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne, Antonio Paolillo, Diana Goehringer, Magnus Jahre |
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Tim Hansmeier, Marco Platzner, David Andrews 0001 |
An FPGA/HMC-Based Accelerator for Resolution Proof Checking. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamil Piszczek, Piotr Janus, Tomasz Kryjak |
The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling Algorithms. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeckson Dellagostin Souza, Anderson Luiz Sartor, Luigi Carro, Mateus Beck Rutzig, Stephan Wong, Antonio C. S. Beck |
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Milind Parelkar, Darshan Jetly |
High Performance UDP/IP 40Gb Ethernet Stack for FPGAs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Fabio Benevenuti, Fernanda Lima Kastensmidt |
Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Junsik Kim 0004, Jaehyun Park 0003 |
FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Augusto G. Erichsen, Anderson Luiz Sartor, Jeckson Dellagostin Souza, Monica Magalhães Pereira, Stephan Wong, Antonio C. S. Beck |
ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Lukas Johannes Jung, Christian Hochberger |
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Bruno da Silva 0001, Laurent Segers, An Braeken, Kris Steenhaut, Abdellah Touhafi |
A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano |
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Uzaif Sharif, Shahnam Mirzaei |
High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Konstantinos Katsantonis, Christoforos Kachris, Dimitrios Soudris |
Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller 0005, Umut Durak, Jürgen Becker 0001 |
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner 0001 |
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazusa Musha, Tomohiro Kudoh, Hideharu Amano |
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Raheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei 0001, Mohammad Alaei, Masoud Daneshtalab |
HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima |
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Panagiotis G. Mousouliotis, Loukas P. Petrou |
SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Osvaldo Navarro, Michael Hübner 0001 |
Runtime Adaptive Cache for the LEON3 Processor. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoforos Kachris, Ioannis Stamelos, Elias Koromilas, Dimitrios Soudris |
Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos S. Voros, Michael Hübner 0001, Georgios Keramidas, Diana Goehringer, Christos P. Antonopoulos, Pedro C. Diniz (eds.) |
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis |
HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Palchaudhuri, Anindya Sundar Dhar |
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis Rizakis, Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis |
Approximate FPGA-Based LSTMs Under Computation Time Constraints. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy 0001 |
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker 0001 |
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Christos P. Antonopoulos, Konstantinos Antonopoulos, Christos Panagiotou, Nikolaos S. Voros |
Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Almabrok Abdoalnasir, Mihalis Psarakis, Anastasios I. Dounis |
An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Oguzhan Sezenlik, Sebastian Schüller, Joachim K. Anlauf |
VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck |
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Benedikt Janßen, Florian Kästner, Tim Wingender, Michael Hübner 0001 |
A Dynamic Partial Reconfigurable Overlay Framework for Python. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kris Heid, Jakob Wenzel 0002, Christian Hochberger |
Fast DSE for Automated Parallelization of Embedded Legacy Applications. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy 0001, Ranjani Narayan |
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Florian Fricke, André Werner 0001, Keyvan Shahin, Michael Hübner 0001 |
CGRA Tool Flow for Fast Run-Time Reconfiguration. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepayan Bhowmik, Kofi Appiah |
Embedded Vision Systems: A Review of the Literature. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Umar Ibrahim Minhas, Roger F. Woods, George Karakonstantis |
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jürgen Becker 0001, Falco K. Bapp |
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jens Rettkowski, Diana Goehringer |
High-Level Synthesis of Software-Defined MPSoCs. |
ARC |
2018 |
DBLP DOI BibTeX RDF |
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