Search results for "DSPs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Riadh Brinci, Walid Khmiri, Mefteh Mbarek, Abdellatif Ben Rabaa, Ammar Bouallègue	Efficient Hardware Design for Computing Pairings Using Few FPGA In-built DSPs.	IACR Cryptol. ePrint Arch.	2015	DBLP BibTeX RDF
21	Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan	Rapid estimation of DSPs utilization for efficient high-level synthesis.	DSP	2015	DBLP DOI BibTeX RDF
21	Andreas Karlsson, Joar Sohl, Dake Liu	Software-based QPP interleaving for baseband DSPs with LUT-accelerated addressing.	DSP	2015	DBLP DOI BibTeX RDF
21	Tao Chi, Ming Chen, Haile Zhao	Binding and scheduling for system-level synthesis of ARM-core with multiple DSPs.	ICACI	2015	DBLP DOI BibTeX RDF
21	John Glossner, Paul Blinzer, Jarmo Takala	HSA-enabled DSPs and accelerators.	GlobalSIP	2015	DBLP DOI BibTeX RDF
21	Florian Grützmacher, Johann-Peter Wolff, Christian Haubelt	Sensor-based online hand gesture recognition on multi-core DSPs.	GlobalSIP	2015	DBLP DOI BibTeX RDF
21	Jiangzhou He, Wen-Guang Chen, Guang-Ri Chen, Wei-Min Zheng, Zhizhong Tang, Handong Ye	OpenMDSP: Extending OpenMP to Program Multi-Core DSPs.	J. Comput. Sci. Technol.	2014	DBLP DOI BibTeX RDF
21	Maribel Castillo, Juan Carlos Fernández 0002, Francisco D. Igual, Antonio Plaza, Enrique S. Quintana-Ortí, Alfredo Remón	Hyperspectral Unmixing on Multicore DSPs: Trading Off Performance for Energy.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2014	DBLP DOI BibTeX RDF
21	Athanasios Kalantzopoulos, Evangelos Zigouris	Online Laboratory Sessions in System Design with DSPs using the R-DSP Lab.	Int. J. Online Eng.	2014	DBLP DOI BibTeX RDF
21	Lijun Xu, Shefeng Yan	Design of Underwater Acoustic Modems through High Performance DSPs.	WUWNet	2014	DBLP DOI BibTeX RDF
21	Taisong Jin, Minwook Ahn, Donghoon Yoo, Dongkwan Suh, Yoonseo Choi, Do Hyung Kim 0002, Shihwa Lee	Nop compression scheme for high speed DSPs based on VLIW architecture.	ICCE	2014	DBLP DOI BibTeX RDF
21	Christoph W. Kessler	Compiling for VLIW DSPs.	Handbook of Signal Processing Systems	2013	DBLP DOI BibTeX RDF
21	Björn Franke	C Compilers and Code Optimization for DSPs.	Handbook of Signal Processing Systems	2013	DBLP DOI BibTeX RDF
21	Tiantian Liu 0001, Yingchao Zhao 0001, Chun Jason Xue, Minming Li	Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory.	IEEE Trans. Signal Process.	2013	DBLP DOI BibTeX RDF
21	Jingtong Hu, Yi He 0001, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chun Jason Xue, Yingchao Zhao 0001	Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory.	J. Syst. Archit.	2013	DBLP DOI BibTeX RDF
21	Shouzhen Gu, Qingfeng Zhuge, Jingtong Hu, Juan Yi, Edwin Hsing-Mean Sha	Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation.	ICASSP	2013	DBLP DOI BibTeX RDF
21	Daniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim	Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os.	ICCAD	2013	DBLP DOI BibTeX RDF
21	Hassan A. Salamy	Minimizing address arithmetic instructions in embedded applications on DSPs.	Comput. Electr. Eng.	2012	DBLP DOI BibTeX RDF
21	Francisco D. Igual, Murtaza Ali, Arnon Friedmann, Eric Stotzer, Timothy Wentz, Robert A. van de Geijn	Unleashing the high-performance and low-power of multi-core DSPs for general-purpose HPC.	SC	2012	DBLP DOI BibTeX RDF
21	Daisuke Suzuki, Tsutomu Matsumoto	How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
21	Sheng Liu 0001, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang 0023, Yaohua Wang	LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
21	Daniel W. Chang, Nam Sung Kim, Michael J. Schulte	Analyzing the performance and energy impact of 3D memory integration on embedded DSPs.	ICSAMOS	2011	DBLP DOI BibTeX RDF
21	Miroslav N. Velev, Ping Gao 0002	Exploiting Abstraction for Efficient Formal Verification of DSPs with Arrays of Reconfigurable Functional Units.	ICFEM	2011	DBLP DOI BibTeX RDF
21	Miroslav N. Velev, Ping Gao 0002	Automatic formal verification of reconfigurable DSPs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
21	Sheng Liu 0001, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen	Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.	NAS	2011	DBLP DOI BibTeX RDF
21	Kai Zhang 0023, Shuming Chen, Sheng Liu 0001, Yaohua Wang, Junhui Huang	Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.	ASICON	2011	DBLP DOI BibTeX RDF
21	Tiantian Liu 0001, Yingchao Zhao 0001, Chun Jason Xue, Minming Li	Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory.	DAC	2011	DBLP DOI BibTeX RDF
21	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2010	DBLP DOI BibTeX RDF
21	Alon Hayim, Michael Knieser, Maher E. Rizkalla	DSPs/FPGAs Comparative Study for Power Consumption, Noise Cancellation, and Real Time High Speed Applications.	J. Softw. Eng. Appl.	2010	DBLP DOI BibTeX RDF
21	Ron Schneiderman	DSPs See Gains in Their Impact on New Medical Imaging Designs [Special Reports].	IEEE Signal Process. Mag.	2010	DBLP DOI BibTeX RDF
21	Ron Schneiderman	DSPs Evolving in Consumer Electronics Applications [Special Reports].	IEEE Signal Process. Mag.	2010	DBLP DOI BibTeX RDF
21	Björn Franke	C Compilers and Code Optimization for DSPs.	Handbook of Signal Processing Systems	2010	DBLP DOI BibTeX RDF
21	Christoph W. Kessler	Compiling for VLIW DSPs.	Handbook of Signal Processing Systems	2010	DBLP DOI BibTeX RDF
21	Meng-Hsuan Cheng, Kenn Slagter, Tai-Wen Lung, Yeh-Ching Chung	A VLIW-Based Post Compilation Framework for Multimedia Embedded DSPs with Hardware Specific Optimizations.	MTPP	2010	DBLP DOI BibTeX RDF
21	Yannis P. Tsividis	Event-driven, continuous-time ADCs and DSPs for adapting power dissipation to signal activity.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Maxime Pelcat	Prototypage Rapide et Génération de Code pour DSP Multi-Coeurs Appliqués à la Couche Physique des Stations de Base 3GPP LTE. (Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs).		2010	RDF
21	Ron Schneiderman	DSPs are helping to make it hard to get lost [Spotlight Report].	IEEE Signal Process. Mag.	2009	DBLP DOI BibTeX RDF
21	LiPing Sun, Zhihui Li, WenHua Cao	Design and Realization of Fuzzy Self-Tuning PID Controller Based on TMS320LF2407A DSPs for Microwave-Vacuum Wood Drying.	FSKD (4)	2009	DBLP DOI BibTeX RDF
21	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
21	Frank Schäfer	Das hermetische Eigenwertproblem: Implementierungsaspekte für Festkomma-SIMD-DSPs.		2008	RDF
21	Muhammad Sohail Sadiq, Shoab Ahmed Khan	Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs.	IEEE Trans. Consumer Electron.	2007	DBLP DOI BibTeX RDF
21	Zoran Nikolic, Ha Thai Nguyen, Gene Frantz	Design and Implementation of Numerical Linear Algebra Algorithms on Fixed Point DSPs.	EURASIP J. Adv. Signal Process.	2007	DBLP DOI BibTeX RDF
21	Peter Dent	CDMA Transmit Acceleration for DSPS in Basestations.	DSP	2007	DBLP DOI BibTeX RDF
21	Jinpyo Hong, J. Ramanujam	Memory Offset Assignment for DSPs.	ICESS	2007	DBLP DOI BibTeX RDF
21	Dong Wang, Xiaowen Chen, Shuming Chen, Xing Fang, Shuwei Sun	FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
21	Charles B. Cameron, Rosa Nivea Rodriguez, Nathan Padgett, Eugene Waluschka, Semion Kizhner, Gabriel Colon, Colleen Weeks	Fast optical ray tracing using multiple DSPs.	IEEE Trans. Instrum. Meas.	2006	DBLP DOI BibTeX RDF
21	Vladimir V. Rubanov, A. I. Grinevich, D. A. Markovtsev	Specific optimization features in a C compiler for DSPs.	Program. Comput. Softw.	2006	DBLP DOI BibTeX RDF
21	Michael Hosemann, Gerhard P. Fettweis	On enhancing SIMD-controlled DSPs for performing recursive filtering.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF
21	Gary Gréwal, Stelian Coros, Mario Ventresca	A Memetic Algorithm for Performing Memory Assignment in Dual-Bank DSPs.	Int. J. Comput. Intell. Appl.	2006	DBLP DOI BibTeX RDF
21	Chun Jason Xue, Zili Shao, Qingfeng Zhuge, Bin Xiao 0001, Meilin Liu, Edwin Hsing-Mean Sha	Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
21	Brendon J. C. Schmidt, Chi Ng, Patrick Yien, Christina Harris, Ushodaya Saripalle, Andrea Price, Simon Brewer, Giuseppe Scelsi, Robert Slaviero, Jean Armstrong	Efficient Algorithms for PAPR Reduction in OFDM Transmitters Implemented using Fixed-Point DSPs.	VTC Spring	2006	DBLP DOI BibTeX RDF
21	Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton, Mario Ventresca	Optimized Memory Assignment for DSPs.	IEEE Congress on Evolutionary Computation	2006	DBLP DOI BibTeX RDF
21	Vincent Brost, Fan Yang 0019, Michel Paindavoine	Embedded System Prototyping Experience Using Multi-DSPs VHDL Model.	ReCoSoC	2006	DBLP BibTeX RDF
21	Antonio Calomarde, Diego Mateo, Antonio Rubio 0001	High level spectral-based analysis of power consumption in DSPs systems.	ISCAS	2006	DBLP DOI BibTeX RDF
21	David Brier, Raj S. Mitra	Use of C/C++ models for architecture exploration and verification of DSPs.	DAC	2006	DBLP DOI BibTeX RDF	simulation, verification, formal, RTL, C/C++
21	Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara	Memory Allocation and Code Optimization Methods for DSPs with Indexed Auto-Modification.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
21	Rajeevan Amirtharajah, Jamie Collier, Jeff Siebert, Bicky Zhou, Anantha P. Chandrakasan	DSPs for energy harvesting sensors: applications and architectures.	IEEE Pervasive Comput.	2005	DBLP DOI BibTeX RDF
21	Randy Allen	Compiling high-level languages to DSPs: automating the implementation path.	IEEE Signal Process. Mag.	2005	DBLP DOI BibTeX RDF
21	Lothar Thiele, Ernesto Wandeler, Samarjit Chakraborty	Performance analysis of multiprocessor DSPs: a stream-oriented component model.	IEEE Signal Process. Mag.	2005	DBLP DOI BibTeX RDF
21	Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek	Design space exploration of coarse-grain reconfigurable DSPs.	ReConFig	2005	DBLP DOI BibTeX RDF
21	Yannis P. Tsividis, Glenn E. R. Cowan, Yee William Li, Kenneth L. Shepard	Continuous-time DSPs, analog/digital computers and other mixed-domain circuits.	ESSCIRC	2005	DBLP DOI BibTeX RDF
21	Kerem Küçük, Mustafa Karakoç, Adnan Kavak, Halil Yigit	Design and Hardware Implementation of a Novel Smart Antenna Algorithm Using TI DSPs.	ISWCS	2005	DBLP DOI BibTeX RDF
21	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.	EUC	2005	DBLP DOI BibTeX RDF	Loop Distribution, Embedded DSP, Scheduling, Code Size, Loop Fusion
21	W. Patrick Hays	DSPs: Back to the Future.	ACM Queue	2004	DBLP DOI BibTeX RDF
21	Matthieu Martel	Validation of assembler programs for DSPs: a static analyzer.	PASTE	2004	DBLP DOI BibTeX RDF	numerical accuracy, abstract interpretation, floating-point numbers
21	Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao 0001	Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.	EUC	2004	DBLP DOI BibTeX RDF
21	Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao 0001	Optimizing Address Assignment for Scheduling Embedded DSPs.	EUC	2004	DBLP DOI BibTeX RDF
21	Johannes Fürtler, Konrad J. Mayer, Werner Krattenthaler, Ivan Bajla	SPOT - Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing.	Real Time Imaging	2003	DBLP DOI BibTeX RDF
21	Gary William Grewal, Thomas Charles Wilson	Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).	Int. J. Comput. Intell. Appl.	2003	DBLP DOI BibTeX RDF
21	Lawrence T. Clark	Trends and challenges for wireless embedded DSPs.	CICC	2003	DBLP DOI BibTeX RDF
21	Thorsten Dräger, Gerhard P. Fettweis	Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs.	ASAP	2003	DBLP DOI BibTeX RDF
21	Ichiro Kuroda	Asynchronous Multirate Real-Time Scheduling for Programmable DSPs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
21	Alice Wang, Anantha P. Chandrakasan	Energy-efficient DSPs for wireless sensor networks.	IEEE Signal Process. Mag.	2002	DBLP DOI BibTeX RDF
21	J. Dido, N. Géraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier	A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.	FPGA	2002	DBLP DOI BibTeX RDF	data-path optimization, floating-point/fixed-point conversion, hardware division, hyardware optimization, FPGA, floating-point, video-processing
21	Mohammed Aziz, Said Boussakta, Desmond C. McLernon	Parallelisation of the 1-D block filter algorithm to run on multiple DSPs.	ICECS	2002	DBLP DOI BibTeX RDF
21	Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono	A low-power W-CDMA demodulator using specially-designed micro-DSPs.	CICC	2002	DBLP DOI BibTeX RDF
21	Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, S. Wolter, Steffen Buch, Marek Wróblewski, Josef A. Nossek	Low power register file architecture for application specific DSPs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
21	Yann Le Mener, Mickaël Raulet, Jean-François Nezan, Apostolos A. Kountouris, Christophe Moy	Syndex executive kernel development for DSPs TI C6X applied to real-time and embedded multiprocessors architectures.	EUSIPCO	2002	DBLP BibTeX RDF
21	Volker Aue, Johannes Kneip, Matthias Weiss, Michael Bolle, Gerhard P. Fettweis	MATLAB based codesign framework for wireless broadband communication DSPs.	ICASSP	2001	DBLP DOI BibTeX RDF
21	Rainer Leupers, Daniel Kotte	Variable partitioning for dual memory bank DSPs.	ICASSP	2001	DBLP DOI BibTeX RDF
21	Abdelaziz Bensrhair, N. Chafiqui, Pierre Miché	Implementation of a 3D Vision System on DSPs TMS320C31.	Real Time Imaging	2000	DBLP DOI BibTeX RDF
21	Klaus Illgner	DSPs for image and video processing.	Signal Process.	2000	DBLP DOI BibTeX RDF
21	Junchen Du, George Warner, Erik J. Vallow, Tom L. Hollenbach	High-performance DSPs.	IEEE Signal Process. Mag.	2000	DBLP DOI BibTeX RDF
21	Thomas J. Wollinger, Min Wang, Jorge Guajardo, Christof Paar	How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP.	AES Candidate Conference	2000	DBLP BibTeX RDF
21	Patrick N. Morgan, Russell J. Iannuzzelli, F. H. Epstein, R. S. Balaban	Real-time cardiac MRI using DSPs.	IEEE Trans. Medical Imaging	1999	DBLP DOI BibTeX RDF
21	Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao 0001, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi	The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF
21	C. Robert Hewes, Periagaram K. Rajasekaran	DSPS education: an industry leader's experiences and expectations.	ICASSP	1999	DBLP DOI BibTeX RDF
21	Amit Rao, Santosh Pande	Storage Assignment Optimizations to Generate Compact and Efficient Code on Embedded DSPs.	PLDI	1999	DBLP DOI BibTeX RDF
21	Vipin Jain, Siddharth Rele, Santosh Pande, J. Ramanujam	Code Restructuring for Improving Real Time Response through Code Speed, Size Trade-offs on Limited Memory Embedded DSPs.	LCPC	1999	DBLP DOI BibTeX RDF
21	M. N. Mahesh, Mahesh Mehendale	Improving performance of high precision signal processing algorithms on programmable DSPs.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
21	Steven Bashford, Rainer Leupers	Constraint Driven Code Selection for Fixed-Point DSPs.	DAC	1999	DBLP DOI BibTeX RDF
21	Vishal Markandey, Wissam Rabadi, Jeremiah Golston, Gene Frantz	Architectures and visual-processing applications of multimedia DSPs.	Int. J. Imaging Syst. Technol.	1998	DBLP DOI BibTeX RDF
21	Manoj Aggarwal, Naresh R. Shanbhag, Narendra Ahuja	Improving the throughput of flexible-precision DSPS via algorithm transformation.	ICASSP	1998	DBLP DOI BibTeX RDF
21	Marlene Wan, Yuji Ichikawa, David Lidsky, Jan M. Rabaey	An energy conscious methodology for early design exploration of heterogeneous DSPs.	CICC	1998	DBLP DOI BibTeX RDF
21	Bryan D. Ackland, Chris Nicol	High performance DSPs - what's hot and what's not?	ISLPED	1998	DBLP DOI BibTeX RDF	architecture, low power, DSP, circuit design
21	Ulrich Kiffmeier, Michael Beine	Block Diagram Based Real-Time Simulation on a Network of Alpha Processors and C40 DSPs.	DIPES	1998	DBLP BibTeX RDF
21	Manuel Mazo 0001, M. Martín, Luciano Boquete, Ignacio Fernández, Felipe Espinosa, M. A. López	System based on digital signal processors (DSPs) for communication between industrial processes with critical time.	Microprocess. Microsystems	1997	DBLP DOI BibTeX RDF
21	Kresimir Cosic, Ivica Kopriva, Tomislav Sikic	A methodology for digital real time simulation of dynamic systems using modern DSPs.	Simul. Pract. Theory	1997	DBLP DOI BibTeX RDF
21	Sanjay Kasturia, Raziel Haimi-Cohen, Colin A. Warwick	DSPs in mobile communication in the United States.	ICASSP	1997	DBLP DOI BibTeX RDF
21	Rita Cucchiara, Alessandro Callipo, Massimo Piccardi	Block processing on multiprocessor DSPs for multimedia applications.	MMSP	1997	DBLP DOI BibTeX RDF